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| REJ09B0397-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 8 H8/3857 Group, H8/3857 F-ZTATTM, H8/3854 Group, H8/3854 F-ZTATTM Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Series H8/3857 H8/3856 H8/3855 H8/3857 F-ZTATTM H8/3854 H8/3853 H8/3852 H8/3854 F-ZTATTM HD6433857, HCD6433857 HD6433856, HCD6433856 HD6433855, HCD6433855 HD64F3857, HCD64F3857 HD6433854, HCD6433854 HD6433853, HCD6433853 HD6433852, HCD6433852 HD64F3854, HCD64F3854 Rev.3.00 Revision date: Jul. 19, 2007 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.3.00 Jul. 19, 2007 page ii of xxiv REJ09B0397-0300 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.3.00 Jul. 19, 2007 page iii of xxiv REJ09B0397-0300 Rev.3.00 Jul. 19, 2007 page iv of xxiv REJ09B0397-0300 Preface The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3857 Group has the following on-chip peripheral functions required for system configuration: a maximum 1,280-dot display LCD controller, four types of timers, a 14-bit PWM, a 2-channel serial communication interface, and an 8-channel A/D converter. The H8/3854 Group has the following on-chip peripheral functions required for system configuration: a maximum 640-dot display LCD controller, three types of timers, a single-channel serial communication interface, and a 4-channel A/D converter. Both series can be used as embedded microcomputers in systems requiring LCD display. The H8/3857, H8/3856, H8/3855, H8/3854, H8/3853, and H8/3852 are available in mask ROM versions, and the H8/3857 and H8/3854 are also available in an F-ZTATTM* version which allows programs to be written after the chip is mounted on a board. Note: * F-ZTAT (Flexible Zero Turn-Around Time) is a trademark of Renesas Technology Corp. This manual describes the hardware of the H8/3857 Group and H8/3854 Group. For details on the H8/3857 Group and H8/3854 Group instruction set, refer to the H8/300L Series Software Manual. Rev.3.00 Jul. 19, 2007 page v of xxiv REJ09B0397-0300 List of Functions Group H8/3857 Group F-ZTAT Version Part No. ROM size (kbytes) RAM size (kbytes) I/O ports Input/output ports Input ports Interrupts External interrupts Internal interrupts Timer A (for realtime clock) Timer B (8 bits) Timer C (8 bits) Timer F (16 bits) Watchdog timer 14-bit PWM Serial communication interface (SCI) A/D converter LCD controller Max. display dots Display RAM size Packages Pins Shipping form x2 8 ch 1280 dots 2048 bits 144 x2 8 ch 1280 dots 2048 bits 144 x2 8 ch 1280 dots 2048 bits 144 x2 8 ch 1280 dots 2048 bits 144 x1 4 ch 640 dots 640 bits 100 x1 4 ch 640 dots 640 bits 100 x1 4 ch 640 dots 640 bits 100 x1 4 ch 640 dots 640 bits 100 Mask ROM Version H8/3854 Group F-ZTAT Version Mask ROM Version H8/3857F H8/3857 H8/3856 H8/3855 60 2 35 9 13 sources 16 sources 60 2 35 9 48 2 35 9 40 2 35 9 H8/3854F H8/3854 H8/3853 H8/3852 60* 2* 24 5 12 sources 14 sources 32* 1* 24 5 24 1* 24 5 16 1* 24 5 13 13 13 sources sources sources 16 16 16 sources sources sources 12 12 12 sources sources sources 14 14 14 sources sources sources FP-144H (20 x 20 mm) TFP-144 (16 x 16 mm) Die (F-ZTAT version: 7.08 x 7.31 mm / mask ROM version: 6.21 x 6.21 mm) FP-100B (14 x 14 mm) TFP-100G (12 x 12 mm) Die (F-ZTAT version: 6.34 x 6.34 mm / mask ROM version: 4.69 x 4.69 mm) Note: * Note that the H8/3854F (F-ZTAT version) and H8/3854 (mask ROM version) have different ROM and RAM sizes. When carrying out program development using the H8/3854F with the intention of mask ROM implementation, care must be taken with ROM and RAM sizes since the maximum sizes for the mask ROM version are 32 kbytes of ROM and 1 kbyte of RAM. Rev.3.00 Jul. 19, 2007 page vi of xxiv REJ09B0397-0300 Main Revisions for This Edition Item All Page Revision (See Manual for Details) * * Company name and brand names amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. Designation for categories amended (Before) H8/3857 Series (After) H8/3857 Group (Before) H8/3854 Series (After) H8/3854 Group Lower address side [H'0000] 2.2.1 General Registers Figure 2.2 Stack Pointer 29 Figure amended Unused area SP (R7) Stack area Upper address side [H'FFFF] 4.3 Subclock Generator Table 4.2 DC Characteristics and Timing 98 Table condition amended (VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F and H8/3857 Group, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to + 75C*, unless otherwise specified, including subactive mode) Table note amended Note: * The guaranteed temperature as an electrical characteristic for die type products is 75C. 6.2.1 Features 120 Description amended * Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. In block erasing, 1-kbyte, 28-kbyte, 16kbyte, and 12-kbyte blocks can be set arbitrarily. 6.5.4 Erase-Verify Mode 143 Description amended After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the ESU bit in FLMCR2 is cleared at least () s later). Rev.3.00 Jul. 19, 2007 Page vii of xxiv REJ09B0397-0300 Item 8.3 Port 2 Page 182 Revision (See Manual for Details) Description amended The UD function multiplexed with the P21 pin is provided only in the H8/3857 Group, and not in the H8/3854 Group. 11.3 Operation Figure 11.2 PWM Output Waveform 314 Figure amended TH = t H1 + t H2 + t H3 + ..... t H64 t f1 = t f2 = t f3 ..... = t f64 15.2.2 DC 409 Characteristics Table15.2 DC Characteristics of H8/3855, H8/3856, and H8/3857 (1) Table15.3 DC 410 Characteristics of H8/3855, H8/3856, and H8/3857 (2) Table note amended Notes: 4. The guaranteed temperature as an electrical characteristic for die type products is 75C. Table amended Item Allowable output low current (per pin) Symbol IOL Allowable IOL output low current (total) Allowable output high current (per pin) -IOH Allowable -IOH output high current (total) Table note amended Notes: 2. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 Page viii of xxiv REJ09B0397-0300 Item 15.2.3 AC Characteristics Table15.4 Control Signal Timing of H8/3855, H8/3856, and H8/3857 Page 412 Revision (See Manual for Details) Table note amended Notes: 3. The guaranteed temperature as an electrical characteristic for die type products is 75C. Table15.5 Serial 413 Interface (SCI1) Timing of H8/3855, H8/3856, and H8/3857 Table15.6 Serial 414 Interface (SCI3) Timing of H8/3855, H8/3856, and H8/3857 15.2.4 A/D Converter Characteristics Table15.7 A/D Converter Characteristics of H8/3855, H8/3856, and H8/3857 15.2.5 LCD Characteristics Table15.8 LCD Characteristics of H8/3855, H8/3856, and H8/3857 Table15.9 Step-Up 417 Circuit Characteristics of H8/3855, H8/3856, and H8/3857 15.4 Output Load Circuit Figure 15.10 Output Load Conditions 422 416 415 Table note amended Note: * The guaranteed temperature as an electrical characteristic for die type products is 75C. Table note amended Note: * The guaranteed temperature as an electrical characteristic for die type products is 75C. Table note amended Notes: 4. The guaranteed temperature as an electrical characteristic for die type products is 75C. Table note amended Notes: 4. The guaranteed temperature as an electrical characteristic for die type products is 75C. Table note amended Notes: 2. The guaranteed temperature as an electrical characteristic for die type products is 75C. Figure amended VCC 2.4 k LSI Chip Output pin 30 pF 12 k Rev.3.00 Jul. 19, 2007 Page ix of xxiv REJ09B0397-0300 Item 16.2.1 Power Supply Voltage and Operating Range (1) Power Supply Voltage vs. Oscillator Frequency Range Page 424 Revision (See Manual for Details) Figure amended 10.0 32.768 fOSC (MHz) 5.0 2.0 2.7* 3.0 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode fW (kHz) 2.7* 3.0 4.0 5.5 VCC (V) * Active mode (medium speed) Note added Note: * The minimum VCC level of the H8/3854F is 3.0 V. (2) Power Supply Voltage vs. Operating Frequency Range 425 Figure amended (MHz) SUB (kHz) 5.0 19.200 16.384 *1 2.5 1.0 0.5 2.7*2 3.0 4.0 } *1 5.5 VCC (V) 9.600 8.192 4.800 4.096 2.7*2 3.0 4.0 *1 *1 5.5 * Active mode (high speed) * Sleep mode (except CPU) VCC (V) * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) 625.0 (kHz) 500.0 312.5 62.5 2.7 3.0 4.0 5.5 VCC (V) * Active mode (medium speed) Note added Notes: 1. In case of external clock only 2. The minimum VCC level of the H8/3854F is 3.0 V. (3) Power Supply Voltage vs. A/D Converter Operating Range Figure amended 5.0 (MHz) (kHz) 625.0 500.0 312.5 2.5 0.5 2.7* 3.0 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode 62.5 2.7 3.0 4.0 5.5 VCC (V) * Active mode (medium speed) Note added Note: * The minimum VCC level of the H8/3854F is 3.0 V. Rev.3.00 Jul. 19, 2007 Page x of xxiv REJ09B0397-0300 Item 16.2.2 DC Characteristics Table 16.2 DC Characteristics of H8/3852, H8/3853, and H8/3854 (1) Page 426 Revision (See Manual for Details) Table condition amended VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*4, including subactive mode, unless otherwise specified. 429 Table note amended Notes: 4. The guaranteed temperature as an electrical characteristic for die type products is 75C. Table 16.3 DC 430 Characteristics of H8/3852, H8/3853, and H8/3854 (2) Table condition amended VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*2, including subactive mode, unless otherwise specified. Table amended Item Allowable output low current (per pin) Symbol IOL Allowable IOL output low current (total) Allowable output high current (per pin) -IOH Allowable -IOH output high current (total) Table note amended Notes: 2. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 Page xi of xxiv REJ09B0397-0300 Item 16.2.3 AC Characteristics Page 431 Revision (See Manual for Details) Description amended Table 16.4 shows the control signal timing, and table 16.5 shows the serial interface timing, of the H8/3852, H8/3853, and H8/3854. Table condition amended VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*3, including subactive mode, unless otherwise specified. Table 16.4 Control Signal Timing of H8/3852, H8/3853, and H8/3854 432 Table note amended Notes: 3. The guaranteed temperature as an electrical characteristic for die type products is 75C. Table 16.5 Serial 433 Interface (SCI3) Timing of H8/3852, H8/3853, and H8/3854 Table condition amended VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*, unless otherwise specified. Table note amended Note: * The guaranteed temperature as an electrical characteristic for die type products is 75C. 16.2.4 A/D Converter Characteristics Table 16.6 A/D Converter Characteristics of H8/3852, H8/3853, and H8/3854 16.2.5 LCD Characteristics Table 16.7 LCD Characteristics of H8/3852, H8/3853, and H8/3854 434 Table condition amended VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*, unless otherwise specified. Table note amended Note: * The guaranteed temperature as an electrical characteristic for die type products is 75C. 435 Table condition amended VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*2, including subactive mode, unless otherwise specified. Table note amended Notes: 2. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 Page xii of xxiv REJ09B0397-0300 Item B.2 Register Descriptions PMR2--Port mode register 2 Page 492 Revision (See Manual for Details) Bit table amended P43 /IRQ 0 pin function switch 0 Functions as P4 3 input pin 1 Functions as IRQ 0 input pin Rev.3.00 Jul. 19, 2007 Page xiii of xxiv REJ09B0397-0300 All trademarks and registered trademarks are the property of their respective owners. Rev.3.00 Jul. 19, 2007 Page xiv of xxiv REJ09B0397-0300 Contents Section 1 Overview............................................................................................................. 1.1 1.2 1.3 Overview........................................................................................................................... Internal Block Diagram..................................................................................................... Pin Arrangement and Functions........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 1 1 6 8 8 20 Section 2 CPU ...................................................................................................................... 27 2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Address Space...................................................................................................... 2.1.3 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 2.2.1 General Registers ................................................................................................. 2.2.2 Control Registers ................................................................................................. 2.2.3 Initial Register Values.......................................................................................... Data Formats ..................................................................................................................... 2.3.1 Data Formats in General Registers ...................................................................... 2.3.2 Memory Data Formats ......................................................................................... Addressing Modes............................................................................................................. 2.4.1 Addressing Modes ............................................................................................... 2.4.2 Effective Address Calculation ............................................................................. Instruction Set ................................................................................................................... 2.5.1 Data Transfer Instructions.................................................................................... 2.5.2 Arithmetic Operations.......................................................................................... 2.5.3 Logic Operations.................................................................................................. 2.5.4 Shift Operations ................................................................................................... 2.5.5 Bit Manipulations................................................................................................. 2.5.6 Branching Instructions ......................................................................................... 2.5.7 System Control Instructions................................................................................. 2.5.8 Block Data Transfer Instruction........................................................................... Basic Operational Timing ................................................................................................. 2.6.1 Access to On-Chip Memory (RAM, ROM)......................................................... 2.6.2 Access to On-Chip Peripheral Modules ............................................................... CPU States ........................................................................................................................ 2.7.1 Overview.............................................................................................................. 2.7.2 Program Execution State...................................................................................... 27 27 28 28 29 29 29 31 31 32 33 34 34 36 40 42 44 45 45 47 51 53 54 55 55 56 57 57 59 2.2 2.3 2.4 2.5 2.6 2.7 Rev.3.00 Jul. 19, 2007 page xv of xxiv REJ09B0397-0300 2.8 2.9 2.7.3 Program Halt State............................................................................................... 2.7.4 Exception-Handling State .................................................................................... Memory Map .................................................................................................................... 2.8.1 Memory Map ....................................................................................................... Application Notes ............................................................................................................. 2.9.1 Notes on Data Access .......................................................................................... 2.9.2 Notes on Bit Manipulation................................................................................... 2.9.3 Notes on Use of the EEPMOV Instruction .......................................................... 59 59 60 60 62 62 64 70 Section 3 Exception Handling ......................................................................................... 71 3.1 3.2 Overview........................................................................................................................... Reset.................................................................................................................................. 3.2.1 Overview.............................................................................................................. 3.2.2 Reset Sequence .................................................................................................... 3.2.3 Interrupt Immediately after Reset ........................................................................ Interrupts........................................................................................................................... 3.3.1 Overview.............................................................................................................. 3.3.2 Interrupt Control Registers .................................................................................. 3.3.3 External Interrupts ............................................................................................... 3.3.4 Internal Interrupts ................................................................................................ 3.3.5 Interrupt Operations ............................................................................................. 3.3.6 Interrupt Response Time...................................................................................... Application Notes ............................................................................................................. 3.4.1 Notes on Stack Area Use ..................................................................................... 3.4.2 Notes on Rewriting Port Mode Registers............................................................. 71 71 71 71 72 73 73 75 83 84 84 89 89 89 90 3.3 3.4 Section 4 Clock Pulse Generators................................................................................... 93 4.1 Overview........................................................................................................................... 4.1.1 Block Diagram..................................................................................................... 4.1.2 System Clock and Subclock................................................................................. System Clock Generator ................................................................................................... Subclock Generator........................................................................................................... Prescalers .......................................................................................................................... Note on Oscillators ........................................................................................................... 93 93 93 94 96 99 100 4.2 4.3 4.4 4.5 Section 5 Power-Down Modes ........................................................................................ 101 5.1 5.2 Overview........................................................................................................................... 5.1.1 System Control Registers..................................................................................... Sleep Mode ....................................................................................................................... 5.2.1 Transition to Sleep Mode..................................................................................... 101 104 107 107 Rev.3.00 Jul. 19, 2007 page xvi of xxiv REJ09B0397-0300 5.3 5.4 5.5 5.6 5.7 5.8 5.2.2 Clearing Sleep Mode............................................................................................ Standby Mode ................................................................................................................... 5.3.1 Transition to Standby Mode................................................................................. 5.3.2 Clearing Standby Mode ....................................................................................... 5.3.3 Oscillator Settling Time after Standby Mode Is Cleared ..................................... 5.3.4 Transition to Standby Mode and Port Pin States.................................................. 5.3.5 Notes on External Input Signal Changes before/after Standby Mode.................. Watch Mode...................................................................................................................... 5.4.1 Transition to Watch Mode ................................................................................... 5.4.2 Clearing Watch Mode .......................................................................................... 5.4.3 Oscillator Settling Time after Watch Mode Is Cleared........................................ 5.4.4 Notes on External Input Signal Changes before/after Watch Mode .................... Subsleep Mode.................................................................................................................. 5.5.1 Transition to Subsleep Mode ............................................................................... 5.5.2 Clearing Subsleep Mode ...................................................................................... Subactive Mode................................................................................................................. 5.6.1 Transition to Subactive Mode .............................................................................. 5.6.2 Clearing Subactive Mode..................................................................................... 5.6.3 Operating Frequency in Subactive Mode............................................................. Active (medium-speed) Mode........................................................................................... 5.7.1 Transition to Active (medium-speed) Mode ........................................................ 5.7.2 Clearing Active (medium-speed) Mode............................................................... 5.7.3 Operating Frequency in Active (medium-speed) Mode....................................... Direct Transfer .................................................................................................................. 5.8.1 Direct Transfer Overview .................................................................................... 5.8.2 Calculation of Direct Transfer Time before Transition........................................ 5.8.3 Notes on External Input Signal Changes before/after Direct Transition.............. 107 108 108 108 108 109 110 111 111 112 112 112 112 112 113 113 113 113 114 114 114 114 114 115 115 116 118 Section 6 ROM..................................................................................................................... 119 6.1 6.2 Overview........................................................................................................................... 6.1.1 Block Diagram ..................................................................................................... Overview of Flash Memory .............................................................................................. 6.2.1 Features................................................................................................................ 6.2.2 Block Diagram ..................................................................................................... 6.2.3 Flash Memory Operating Modes ......................................................................... 6.2.4 Pin Configuration................................................................................................. 6.2.5 Register Configuration......................................................................................... Flash Memory Register Descriptions................................................................................ 6.3.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 6.3.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 119 119 120 120 121 122 125 126 126 126 129 6.3 Rev.3.00 Jul. 19, 2007 page xvii of xxiv REJ09B0397-0300 6.3.3 Erase Block Register (EBR) ................................................................................ 6.3.4 Mode Control Register (MDCR) ......................................................................... 6.3.5 System Control Register 3 (SYSCR3) ................................................................. 6.4 On-Board Programming Modes........................................................................................ 6.4.1 Boot Mode ........................................................................................................... 6.4.2 User Program Mode............................................................................................. 6.5 Flash Memory Programming/Erasing ............................................................................... 6.5.1 Program Mode ..................................................................................................... 6.5.2 Program-Verify Mode.......................................................................................... 6.5.3 Erase Mode .......................................................................................................... 6.5.4 Erase-Verify Mode .............................................................................................. 6.6 Flash Memory Protection.................................................................................................. 6.6.1 Hardware Protection ............................................................................................ 6.6.2 Software Protection.............................................................................................. 6.6.3 Error Protection.................................................................................................... 6.7 Interrupt Handling during Flash Memory Programming and Erasing .............................. 6.8 Flash Memory Writer Mode ............................................................................................. 6.8.1 Writer Mode Setting ............................................................................................ 6.8.2 Socket Adapter and Memory Map ....................................................................... 6.8.3 Writer Mode Operation........................................................................................ 6.8.4 Memory Read Mode ............................................................................................ 6.8.5 Auto-Program Mode ............................................................................................ 6.8.6 Auto-Erase Mode................................................................................................. 6.8.7 Status Read Mode ................................................................................................ 6.8.8 Status Polling ....................................................................................................... 6.8.9 Writer Mode Transition Time.............................................................................. 6.8.10 Notes on Memory Programming.......................................................................... 6.9 Flash Memory Programming and Erasing Precautions ..................................................... 6.10 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions 130 131 131 132 133 138 140 140 141 143 143 145 145 146 146 148 149 149 149 153 154 158 160 161 162 163 163 164 166 Section 7 RAM..................................................................................................................... 167 7.1 Overview........................................................................................................................... 167 7.1.1 Block Diagram..................................................................................................... 167 Section 8 I/O Ports .............................................................................................................. 169 8.1 8.2 Overview........................................................................................................................... Port 1................................................................................................................................. 8.2.1 Overview.............................................................................................................. 8.2.2 Register Configuration and Description............................................................... 8.2.3 Pin Functions ....................................................................................................... 169 172 172 173 178 Rev.3.00 Jul. 19, 2007 page xviii of xxiv REJ09B0397-0300 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.2.4 Pin States.............................................................................................................. 8.2.5 MOS Input Pull-Up.............................................................................................. Port 2................................................................................................................................. 8.3.1 Overview.............................................................................................................. 8.3.2 Register Configuration and Description............................................................... 8.3.3 Pin Functions ....................................................................................................... 8.3.4 Pin States.............................................................................................................. Port 3 (H8/3857 Group Only) ........................................................................................... 8.4.1 Overview.............................................................................................................. 8.4.2 Register Configuration and Description............................................................... 8.4.3 Pin Functions ....................................................................................................... 8.4.4 Pin States.............................................................................................................. 8.4.5 MOS Input Pull-Up.............................................................................................. Port 4................................................................................................................................. 8.5.1 Overview.............................................................................................................. 8.5.2 Register Configuration and Description............................................................... 8.5.3 Pin Functions ....................................................................................................... 8.5.4 Pin States.............................................................................................................. Port 5................................................................................................................................. 8.6.1 Overview.............................................................................................................. 8.6.2 Register Configuration and Description............................................................... 8.6.3 Pin Functions ....................................................................................................... 8.6.4 Pin States.............................................................................................................. 8.6.5 MOS Input Pull-Up.............................................................................................. Port 9 [Chip-Internal I/O port] .......................................................................................... 8.7.1 Overview.............................................................................................................. 8.7.2 Register Configuration and Description............................................................... 8.7.3 Pin Functions ....................................................................................................... 8.7.4 Pin States.............................................................................................................. Port A [Chip-Internal I/O port] ......................................................................................... 8.8.1 Overview.............................................................................................................. 8.8.2 Register Configuration and Description............................................................... 8.8.3 Pin Functions ....................................................................................................... 8.8.4 Pin States.............................................................................................................. Port B ................................................................................................................................ 8.9.1 Overview.............................................................................................................. 8.9.2 Register Configuration and Description............................................................... 181 182 182 182 183 187 188 189 189 189 192 193 193 194 194 194 196 197 197 197 198 200 200 200 201 201 201 202 203 203 203 204 205 205 206 206 207 Section 9 Timers .................................................................................................................. 209 9.1 Overview........................................................................................................................... 209 Rev.3.00 Jul. 19, 2007 page xix of xxiv REJ09B0397-0300 9.2 9.3 9.4 9.5 9.6 Timer A............................................................................................................................. 9.2.1 Overview.............................................................................................................. 9.2.2 Register Descriptions ........................................................................................... 9.2.3 Timer Operation................................................................................................... 9.2.4 Timer A Operation States .................................................................................... Timer B ............................................................................................................................. 9.3.1 Overview.............................................................................................................. 9.3.2 Register Descriptions ........................................................................................... 9.3.3 Timer Operation................................................................................................... 9.3.4 Timer B Operation States..................................................................................... Timer C (H8/3857 Group Only) ....................................................................................... 9.4.1 Overview.............................................................................................................. 9.4.2 Register Descriptions ........................................................................................... 9.4.3 Timer Operation................................................................................................... 9.4.4 Timer C Operation States..................................................................................... Timer F ............................................................................................................................. 9.5.1 Overview.............................................................................................................. 9.5.2 Register Descriptions ........................................................................................... 9.5.3 Interface with the CPU......................................................................................... 9.5.4 Timer Operation................................................................................................... 9.5.5 Application Notes ................................................................................................ Watchdog Timer [H8/3857F and H8/3854F Only]........................................................... 9.6.1 Overview.............................................................................................................. 9.6.2 Register Descriptions ........................................................................................... 9.6.3 Operation ............................................................................................................. 9.6.4 Watchdog Timer Operating Modes...................................................................... 210 210 212 214 215 215 215 217 219 220 220 220 222 224 226 226 226 229 235 238 240 241 241 243 246 247 Section 10 Serial Communication Interface ................................................................ 249 10.1 Overview........................................................................................................................... 249 10.2 SCI1 (H8/3857 Group Only)............................................................................................. 250 10.2.1 Overview.............................................................................................................. 250 10.2.2 Register Descriptions ........................................................................................... 252 10.2.3 Operation ............................................................................................................. 256 10.2.4 Interrupts.............................................................................................................. 259 10.2.5 Application Notes ................................................................................................ 259 10.3 SCI3 .................................................................................................................................. 260 10.3.1 Overview.............................................................................................................. 260 10.3.2 Register Descriptions ........................................................................................... 262 10.3.3 Operation ............................................................................................................. 279 10.3.4 Operation in Asynchronous Mode ....................................................................... 283 Rev.3.00 Jul. 19, 2007 page xx of xxiv REJ09B0397-0300 10.3.5 10.3.6 10.3.7 10.3.8 Operation in Synchronous Mode ......................................................................... Multiprocessor Communication Function............................................................ Interrupts.............................................................................................................. Application Notes ................................................................................................ 292 299 305 306 Section 11 14-Bit PWM (H8/3857 Group Only) ....................................................... 311 11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram ..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Register Configuration......................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 PWM Control Register (PWCR).......................................................................... 11.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................ 11.3 Operation........................................................................................................................... 311 311 311 312 312 312 312 313 314 Section 12 A/D Converter................................................................................................. 315 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 A/D Result Register (ADRR) .............................................................................. 12.2.2 A/D Mode Register (AMR) ................................................................................. 12.2.3 A/D Start Register (ADSR).................................................................................. 12.3 Operation........................................................................................................................... 12.3.1 A/D Conversion Operation .................................................................................. 12.3.2 Start of A/D Conversion by External Trigger Input............................................. 12.4 Interrupts ........................................................................................................................... 12.5 Typical Use ....................................................................................................................... 12.6 Application Notes ............................................................................................................. 315 315 316 317 317 318 318 318 320 321 321 321 322 322 325 327 327 327 328 329 330 330 Section 13 Dot Matrix LCD Controller (H8/3857 Group) ...................................... 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram ..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ Rev.3.00 Jul. 19, 2007 page xxi of xxiv REJ09B0397-0300 13.2.1 Index Register (IR) .............................................................................................. 13.2.2 Control Register 1 (LR0) ..................................................................................... 13.2.3 Control Register 2 (LR1) ..................................................................................... 13.2.4 Address Register (LR2) ....................................................................................... 13.2.5 Frame Frequency Setting Register (LR3) ............................................................ 13.2.6 Display Data Register (LR4)................................................................................ 13.2.7 Display Start Line Register (LR5) ....................................................................... 13.2.8 Blink Register (LR6)............................................................................................ 13.2.9 Blink Start Line Register (LR8)........................................................................... 13.2.10 Blink End Line Register (LR9)............................................................................ 13.2.11 Contrast Control Register (LRA)......................................................................... 13.3 Operation .......................................................................................................................... 13.3.1 System Overview................................................................................................. 13.3.2 CPU Interface ...................................................................................................... 13.3.3 LCD Drive Pin Functions .................................................................................... 13.3.4 Display Memory Configuration and Display....................................................... 13.3.5 Display Data Output ............................................................................................ 13.3.6 Register and Display Memory Access ................................................................. 13.3.7 Scroll Function..................................................................................................... 13.3.8 Blink Function ..................................................................................................... 13.3.9 Module Standby Mode......................................................................................... 13.3.10 Power-On and Power-Off Procedures.................................................................. 13.3.11 Power Supply Circuit........................................................................................... 13.3.12 LCD Drive Power Supply Voltages..................................................................... 13.3.13 LCD Voltage Generation Circuit ......................................................................... 13.3.14 Contrast Control Circuit....................................................................................... 13.3.15 LCD Drive Bias Selection Circuit ....................................................................... 330 331 333 335 336 338 338 339 339 340 340 342 342 343 346 347 349 353 356 358 360 361 362 363 365 373 374 375 375 375 376 377 377 378 378 378 379 381 382 Section 14 Dot Matrix LCD Controller (H8/3854 Group) ...................................... 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions ........................................................................................................ 14.2.1 Index Register (IR) .............................................................................................. 14.2.2 Control Register 1 (LR0) ..................................................................................... 14.2.3 Control Register 2 (LR1) ..................................................................................... 14.2.4 Address Register (LR2) ....................................................................................... 14.2.5 Frame Frequency Setting Register (LR3) ............................................................ Rev.3.00 Jul. 19, 2007 page xxii of xxiv REJ09B0397-0300 14.2.6 Display Data Register (LR4)................................................................................ 14.3 Operation........................................................................................................................... 14.3.1 System Overview ................................................................................................. 14.3.2 CPU Interface....................................................................................................... 14.3.3 LCD Drive Pin Functions .................................................................................... 14.3.4 Display Memory Configuration and Display ....................................................... 14.3.5 Display Data Output ............................................................................................ 14.3.6 Register and Display Memory Access ................................................................. 14.3.7 Module Standby Mode......................................................................................... 14.3.8 Power-On and Power-Off Procedures.................................................................. 14.3.9 Power Supply Circuit ........................................................................................... 14.3.10 LCD Drive Power Supply Voltages..................................................................... 14.3.11 LCD Voltage Generation Circuit ......................................................................... 14.3.12 LCD Drive Bias Selection Circuit........................................................................ 383 384 384 385 388 389 390 391 395 396 396 397 399 402 Section 15 Electrical Characteristics (H8/3857 Group) ........................................... 403 15.1 H8/3855, H8/3856, and H8/3857 Absolute Maximum Ratings (Standard Specifications) .................................................................................................. 15.2 H8/3855, H8/3856, and H8/3857 Electrical Characteristics (Standard Specifications) .... 15.2.1 Power Supply Voltage and Operating Range....................................................... 15.2.2 DC Characteristics ............................................................................................... 15.2.3 AC Characteristics ............................................................................................... 15.2.4 A/D Converter Characteristics ............................................................................. 15.2.5 LCD Characteristics............................................................................................. 15.2.6 Flash Memory Characteristics.............................................................................. 15.3 Operation Timing.............................................................................................................. 15.4 Output Load Circuit .......................................................................................................... 15.5 Usage Note........................................................................................................................ 403 404 404 406 411 415 416 418 419 422 422 Section 16 Electrical Characteristics (H8/3854 Group) ........................................... 423 16.1 H8/3852, H8/3853, and H8/3854 Absolute Maximum Ratings (Standard Specifications) .................................................................................................. 16.2 H8/3852, H8/3853, and H8/3854 Electrical Characteristics (Standard Specifications) .... 16.2.1 Power Supply Voltage and Operating Range....................................................... 16.2.2 DC Characteristics ............................................................................................... 16.2.3 AC Characteristics ............................................................................................... 16.2.4 A/D Converter Characteristics ............................................................................. 16.2.5 LCD Characteristics............................................................................................. 16.2.6 Flash Memory Characteristics.............................................................................. 16.3 Operation Timing.............................................................................................................. 423 424 424 426 431 434 435 436 437 Rev.3.00 Jul. 19, 2007 page xxiii of xxiv REJ09B0397-0300 16.4 Output Load Circuit .......................................................................................................... 438 16.5 Usage Note........................................................................................................................ 439 Appendix A CPU Instruction Set.................................................................................... 441 A.1 A.2 A.3 Instructions........................................................................................................................ 441 Operation Code Map......................................................................................................... 450 Number of Execution States ............................................................................................. 452 Appendix B Internal I/O Registers ................................................................................. 459 B.1 Register Addresses............................................................................................................ B.1.1 H8/3857 Group Addresses................................................................................... B.1.2 H8/3854 Group Addresses................................................................................... Register Descriptions ........................................................................................................ 459 459 464 468 B.2 Appendix C I/O Port Block Diagrams........................................................................... 508 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 Block Diagram of Port 1 ................................................................................................... Block Diagram of Port 2 ................................................................................................... Block Diagram of Port 3 (H8/3857 Group Only).............................................................. Block Diagram of Port 4 ................................................................................................... Block Diagram of Port 5 ................................................................................................... Block Diagram of Port 9 ................................................................................................... Block Diagram of Port A .................................................................................................. Block Diagram of Port B .................................................................................................. 508 513 516 520 523 524 525 526 Appendix D Port States in the Different Processing States..................................... 527 Appendix E List of Product Codes................................................................................. 528 Appendix F Package Dimensions ................................................................................... 529 Rev.3.00 Jul. 19, 2007 page xxiv of xxiv REJ09B0397-0300 1. Overview Section 1 Overview 1.1 Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3857 Group and H8/3854 Group feature on-chip liquid crystal display (LCD) controllers. Other on-chip peripheral functions include a LCD controller, timers, serial communication interface, and an analog-to-digital (A/D) converter. Together these functions make the H8/3857 Group and H8/3854 Group ideally suited for embedded control of systems requiring an LCD display. The H8/3857 Group comprises the H8/3855, with 40 kbytes of ROM and 2 kbytes of RAM onchip, the H8/3856, with 48 kbytes of ROM and 2 kbytes of RAM, and the H8/3857, with 60 kbytes of ROM and 2 kbytes of RAM. H8/3854 Group mask ROM versions are the H8/3852, with 16 kbytes of ROM and 1 kbyte of RAM on-chip, the H8/3853, with 24 kbytes of ROM and 1 kbyte of RAM, and the H8/3854, with 32 kbytes of ROM and 1 kbyte of RAM. Two F-ZTAT versions--the H8/3857F and H8/3854F--are also available, with userprogrammable on-chip flash ROM. These models have 60 kbytes of ROM and 2 kbytes of RAM. Note that the H8/3854 mask ROM and F-ZTAT versions have different ROM and RAM sizes. Table 1.1 summarizes the features of the H8/3857 Group and H8/3854 Group. Rev.3.00 Jul. 19, 2007 page 1 of 532 REJ09B0397-0300 1. Overview Table 1.1 Item CPU Features Description High-speed H8/300L CPU * General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) Operating speed Max. operating speed: 5 MHz Add/subtract: 0.4 s (operating at 5 MHz) Multiply/divide: 2.8 s (operating at 5 MHz) Can run on 32.768 kHz subclock Instruction set compatible with H8/300 CPU Instruction length of 2 bytes or 4 bytes Basic arithmetic operations between registers MOV instruction for data transfer between memory and registers Multiply (8 bits x 8 bits) Divide (16 bits / 8 bits) Bit accumulator Register-indirect designation of bit position * * Typical instructions * * * * Interrupts H8/3857 Group: 29 interrupt sources * 13 external interrupt sources: IRQ4 to IRQ0, WKP7 to WKP0 * 16 internal interrupt sources H8/3854 Group: 26 interrupt sources * * * * 12 external interrupt sources: IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0 14 internal interrupt sources System clock pulse generator: 1 to 10 MHz Subclock pulse generator: 32.768 kHz Sleep mode Standby mode Watch mode Subsleep mode Subactive mode Active (medium-speed) mode Clock pulse generators Two on-chip clock pulse generators Power-down modes Six power-down modes * * * * * * Rev.3.00 Jul. 19, 2007 page 2 of 532 REJ09B0397-0300 1. Overview Item Memory Description H8/3857 Group * H8/3855: 40-kbyte ROM, 2-kbyte RAM * H8/3856: 48-kbyte ROM, 2-kbyte RAM * H8/3857: 60-kbyte ROM, 2-kbyte RAM * H8/3857F: 60-kbyte ROM, 2-kbyte RAM H8/3854 Group * H8/3852: 16-kbyte ROM, 1-kbyte RAM * H8/3853: 24-kbyte ROM, 1-kbyte RAM * H8/3854: 32-kbyte ROM, 1-kbyte RAM * H8/3854F: 60-kbyte ROM, 2-kbyte RAM Note that the H8/3854 (mask ROM version) and H8/3854F (F-ZTAT version) have different ROM and RAM sizes. I/O ports H8/3857 Group: 44 I/O port pins * I/O pins: 35 * Input pins: 9 H8/3854 Group: 29 I/O port pins * * Timers * I/O pins: 24 Input pins: 5 Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock ()*1 and four clock signals divided from the 1 watch clock (w)* Timer B: 8-bit timer Count-up timer with selection of seven internal clock signals or event input from external pin Auto-reloading Timer C: 8-bit timer (in H8/3857 Group only) Count-up/count-down timer with selection of seven internal clock signals or event input from external pin Auto-reloading Timer F: 16-bit timer Can be used as two independent 8-bit timers. Count-up timer with selection of four internal clock signals or event input from external pin Compare-match function with toggle output Four on-chip timers (three in the H8/3854 Group) * * * Rev.3.00 Jul. 19, 2007 page 3 of 532 REJ09B0397-0300 1. Overview Item Serial communication interface Description H8/3857 Group: Two channels on chip * * SCI1: synchronous serial interface Choice of 8-bit or 16-bit data transfer SCI3: 8-bit synchronous or asynchronous serial interface Built-in function for multiprocessor communication SCI3: 8-bit synchronous or asynchronous serial interface Built-in function for multiprocessor communication H8/3854 Group: One channel on chip * 14-bit PWM Pulse-division PWM output for reduced ripple (in H8/3857 Group only) * Can be used as a 14-bit D/A converter by connecting to an external low-pass filter. A/D converter H8/3857 Group * Successive approximations using a resistance ladder resolution: 8 bits * 8-channel analog input port * Conversion time: 31/ or 62/ per channel H8/3854 Group * * * LCD controller * Successive approximations using a resistance ladder resolution: 8 bits 4-channel analog input port Conversion time: 31/ or 62/ per channel H8/3857 Group: Up to 64 segment pins and 32 common pins Choice of three duty cycles (1/8, 1/16, 1/32) With 1/8 duty selected: 64 SEG x 8 COM, 40 SEG x 8 COM With 1/16 duty selected: 56 SEG x 16 COM, 40 SEG x 16 COM With 1/32 duty selected: 40 SEG x 32 COM * Built-in 2048-bit display data RAM * Built-in 2x or 3x LCD step-up circuit * Built-in contrast control circuit * Built-in LCD power supply bleeder resistance and voltage follower opamp circuits H8/3854 Group: 40 segment pins and up to 16 common pins * Choice of two duty cycles (1/8, 1/16) With 1/8 duty selected: 40 SEG x 8 COM With 1/16 duty selected: 40 SEG x 16 COM Built-in 640-bit display data RAM Built-in LCD power supply bleeder resistance * * Rev.3.00 Jul. 19, 2007 page 4 of 532 REJ09B0397-0300 1. Overview Item Product lineup Description H8/3857 Group Part No. Mask ROM Version HD6433855FQ HD6433855TG HCD6433855 HD6433856FQ HD6433856TG HCD6433856 HD6433857FQ HD6433857TG HCD6433857 F-ZTAT Version HD64F3857FQ HD64F3857TG HCD64F3857 Package 144-pin QFP (FP-144H) 144-pin TQFP (TFP-144) Die 144-pin QFP (FP-144H) 144-pin TQFP (TFP-144) Die 144-pin QFP (FP-144H) 144-pin TQFP (TFP-144) Die ROM: 60 kbytes RAM: 2 kbytes ROM: 48 kbytes RAM: 2 kbytes ROM/RAM Size ROM: 40 kbytes RAM: 2 kbytes H8/3854 Group Part No. Mask ROM 2 Version* HD6433852H HD6433852W HCD6433852 HD6433853H HD6433853W HCD6433853 HD6433854H HD6433854W HCD6433854 F-ZTAT Version HD64F3854H HD64F3854W HCD64F3854 Package 100-pin QFP (FP-100B) ROM/RAM Size ROM: 16 kbytes 100-pin TQFP (TFP-100G) RAM: 1 kbyte Die 100-pin QFP (FP-100B) ROM: 24 kbytes 100-pin TQFP (TFP-100G) RAM: 1 kbyte Die 100-pin QFP (FP-100B) ROM: 32 kbytes 100-pin TQFP (TFP-100G) RAM: 1 kbyte Die 100-pin QFP (FP-100B) ROM: 60 kbytes 100-pin TQFP (TFP-100G) RAM: 2 kbytes Die Notes: 1. and w are defined in section 4, Clock Pulse Generators. 2. Under development Rev.3.00 Jul. 19, 2007 page 5 of 532 REJ09B0397-0300 1. Overview 1.2 Internal Block Diagram Figures 1.1 and 1.2 show internal block diagrams of the H8/3857 Group and H8/3854 Group. OSC1 OSC2 RES TEST2 TEST FWE X1 X2 System clock oscillator Subclock oscillator VCC VSS VSS CPU (8-bit) Address bus FLASH/ MASK ROM RAM Data bus (upper) P10/TMOW P11/TMOFL P12/TMOFH P13 P14/PWM P15/IRQ1/TMIB P16/IRQ2/TMIC P17/IRQ3/TMIF P20/IRQ4/ADTRG P21/UD P22 P23 P24 P25 P26 P27 P30/SCK1 P31/SI1 P32/SO1 P33 P34 P35 P36 P37 Data bus (lower) Port 1 Port 2 Timer B SCI3 Port 5 RS R/W STRB PA3 PA2 PA1 PA0 Timer A SCI1 P57/WKP7 P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 AVCC AVSS Port 3 A/D Timer F P40/SCK3 P41/RXD P42/TXD P43/IRQ0 Port 4 14-bit PWM Port 9 P97 P96 P95 P94 P93 P92 P91 P90 Port A Internal I/O port V5OUT V4OUT V3OUT V2OUT V1OUT V4 V34 V3 VLCD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Port B Timer C LCD VLOUT C1- C1+ C2- C2+ VCi *** *** SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 *** *** COM29/SEG44 COM30/SEG43 COM31/SEG42 COM32/SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9/SEG64 COM10/SEG63 COM11/SEG62 COM12/SEG61 COM13/SEG60 COM14/SEG59 COM15/SEG58 COM16/SEG57 Figure 1.1 H8/3857 Group Internal Block Diagram Rev.3.00 Jul. 19, 2007 page 6 of 532 REJ09B0397-0300 1. Overview OSC1 OSC2 System clock oscillator Subclock oscillator CPU (8-bit) FLASH/ MASK ROM RAM Address bus P10/TMOW P11/TMOFL P12/TMOFH P15/IRQ1/TMIB P17/IRQ3/TMIF Data bus (upper) Data bus (lower) Port 1 RES TEST2 TEST FWE X1 X2 VCC VSS P20/IRQ4/ADTRG P21 P22 P23 P24 P25 P26 P27 Port 2 Timer B SCI3 A/D P40/SCK3 P41/RXD P42/TXD P43/IRQ0 Port 4 Port 9 P97 P96 P95 P94 P93 P92 P91 P90 Port A PA3 PA2 PA1 PA0 Internal I/O port V1OUT V2OUT V3OUT V4OUT V5OUT LCD ... ... COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 Figure 1.2 H8/3854 Group Internal Block Diagram Rev.3.00 Jul. 19, 2007 page 7 of 532 REJ09B0397-0300 RS R/W STRB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Port B Timer F Port 5 Timer A P57/WKP7 P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 1. Overview 1.3 1.3.1 Pin Arrangement and Functions Pin Arrangement The pin arrangements of the H8/3857 Group and H8/3854 Group are shown in figures 1.3 and 1.4. The HCD64F3857 pad layout is shown in figure 1.5, and the pad coordinates in table 1.2; the HCD6433855, HCD6433856, and HCD6433857 pad layout is shown in figure 1.6, and the pad coordinates in table 1.3; the HCD64F3854 pad layout is shown in figure 1.7, and the pad coordinates in table 1.4; and the HCD6433852, HCD6433853, and HCD6433854 pad layout is shown in figure 1.8, and the pad coordinates in table 1.5. COM17/SEG56 COM18/SEG55 COM19/SEG54 COM20/SEG53 COM21/SEG52 COM22/SEG51 COM23/SEG50 COM24/SEG49 COM25/SEG48 COM26/SEG47 COM27/SEG46 COM28/SEG45 COM29/SEG44 COM30/SEG43 COM31/SEG42 COM32/SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 V5OUT V4OUT V3OUT V2OUT V1OUT V4 V34 V3 VCi C2- C2+ C1- C1+ VLOUT VLCD VSS P37 P36 P35 P34 P33 P32/SO1 P31/SI1 P30/SCK1 P17/IRQ3/TMIF P16/IRQ2/TMIC P15/IRQ1/TMIB P14/PWM P13 P12/TMOFH P11/TMOFL P10/TMOW P43/IRQ0 P42/TXD P41/RXD P40/SCK3 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 H8/3857 (Top view) FP-144H TFP-144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM16/SEG57 COM15/SEG58 COM14/SEG59 COM13/SEG60 COM12/SEG61 COM11/SEG62 COM10/SEG63 COM9/SEG64 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 Figure 1.3 H8/3857 Group Pin Arrangement (FP-144H, TFP-144: Top View) Rev.3.00 Jul. 19, 2007 page 8 of 532 REJ09B0397-0300 P57/WKP7 P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 P27 P26 P25 P24 P23 P22 P21/UD P20/IRQ4/ADTRG AVCC PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 AVSS X2 X1 VSS OSC2 OSC1 TEST TEST2 VCC RES FWE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1. Overview SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 V5OUT V4OUT V3OUT V2OUT V1OUT P17/IRQ3/TMIF P15/IRQ1/TMIB P12/TMOFH P11/TMOFL P10/TMOW P43/IRQ0 P42/TXD P41/RXD P40/SCK3 P57/WKP7 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 H8/3854 (Top view) FP-100B TFP-100G SEG5 SEG4 SEG3 SEG2 SEG1 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 Figure 1.4 H8/3854 Group Pin Arrangement (FP-100B, TFP-100G: Top View) P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 P27 P26 P25 P24 P23 P22 P21 P20/IRQ4/ADTRG TEST2 X2 X1 VSS OSC2 OSC1 TEST VCC RES FWE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Rev.3.00 Jul. 19, 2007 page 9 of 532 REJ09B0397-0300 1. Overview Y 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 1 2 3 4 4-2 5 5-2 6 6-2 Model 7 7-2 8 9 10 11 12 13 14 15 (0, 0) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 39 41 43 45 71 47 49 51 53 55 57 59 61 63 65 67 69 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 X Model: HD64F3857 Chip size: 7.08 mm x 7.31 mm Figure 1.5 Pad Layout of HCD64F3857 (F-ZTAT Version) (Top View) Rev.3.00 Jul. 19, 2007 page 10 of 532 REJ09B0397-0300 1. Overview Table 1.2 Pad No. Pad Name 1 2 3 4 4-2 5 5-2 6 6-2 7 7-2 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 P57 /WKP7 P56 /WKP6 P55 /WKP5 P54 /WKP4 NC4* 2 HCD64F3857 Pad Coordinates Coordinates*1 X (m) Y (m) -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 2928 2784 2640 2506 2372 2238 2044 1854 1720 1590 1456 1316 1173 1039 905 771 637 503 369 235 22 -143 -273 -403 -533 -663 -793 -923 -1053 -1228 -1438 -1568 -1763 -1981 -2134 Pad No. Pad Name 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 TEST TEST2 VCC RES FWE COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9/SEG64 COM10/SEG63 COM11/SEG62 COM12/SEG61 COM13/SEG60 COM14/SEG59 COM15/SEG58 COM16/SEG57 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 Coordinates*1 X (m) Y (m) -3348 -3348 -3348 -3348 -3348 -2862 -2700 -2536 -2374 -2210 -2046 -1884 -1720 -1556 -1394 -1231 -1069 -905 -741 -579 -415 -251 -89 75 237 401 565 727 891 1055 1217 1380 1542 1706 1870 -2264 -2404 -2599 -2794 -2944 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 -3463 Pad No. Pad Name 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 COM32/SEG41 COM31/SEG42 COM30/SEG43 COM29/SEG44 COM28/SEG45 COM27/SEG46 COM26/SEG47 Coordinates*1 X (m) Y (m) 2032 2196 2360 2522 2686 2848 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 3348 -3463 -3463 -3463 -3463 -3463 -3463 -2907 -2747 -2587 -2427 -2267 -2107 -1947 -1787 -1627 -1467 -1307 -1148 -988 -828 -668 -508 -348 -188 -28 132 292 452 612 772 932 1092 1252 1411 1571 P53 /WKP3 NC3*2 P52 /WKP2 NC2*2 P51 /WKP1 NC1*2 P50 /WKP0 P27 P26 P25 P24 P23 P22 P21 /UD P20 /IRQ4 /ADTRG -3348 AVCC PB0 /AN0 PB1 /AN1 PB2 /AN2 PB3 /AN3 PB4 /AN4 PB5 /AN5 PB6 /AN6 PB7 /AN7 AVSS X2 X1 VSS OSC2 OSC1 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 -3348 100 COM25/SEG48 101 COM24/SEG49 Rev.3.00 Jul. 19, 2007 page 11 of 532 REJ09B0397-0300 1. Overview Pad No. Pad Name 102 COM23/SEG50 103 COM22/SEG51 104 COM21/SEG52 105 COM20/SEG53 106 COM19/SEG54 107 COM18/SEG55 108 COM17/SEG56 109 V5OUT 110 V4OUT 111 V3OUT 112 V2OUT 113 V1OUT 114 V4 115 V34 116 V3 Coordinates*1 X (m) Y (m) 3348 3348 3348 3348 3348 3348 3348 2776 2616 2456 2296 2136 1976 1816 1656 1731 2063 2223 2383 2543 2703 2863 3463 3463 3463 3463 3463 3463 3463 3463 Pad No. Pad Name 117 Vci 118 C2- 119 C2+ 120 C1- 121 C1+ 122 VLOUT 123 VLCD 124 VSS 125 P37 126 P36 127 P35 128 P34 129 P33 130 P32 /SO1 131 P31 /Sl1 Coordinates*1 X (m) Y (m) 1471 1341 1125 925 747 569 395 226 74 -78 -234 -386 -538 -690 -848 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 Pad No. Pad Name 132 P30 /SCK1 133 P17 /IRQ3/TMIF 134 P16 /IRQ2/TMIC 135 P15 /IRQ1/TMIB 136 P14 /PWM 137 P13 138 P12 /TMOFH 139 P11 /TMOFL 140 P10 /TMOW 141 P43 /IRQ0 142 P42 /TXD 143 P41 /RXD 144 P40 /SCK3 Coordinates*1 X (m) Y (m) -982 -1116 -1250 -1383 -1611 -1761 -1911 -2045 -2180 -2447 -2587 -2737 -2888 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 3463 Notes: 1. Numbers indicate coordinates at the center of the pad area, with an accuracy of 5 m. The origin is the center of the chip, and the center is at a point halfway between pads, horizontally and vertically. 2. NC1 to NC4 are test pads; they should be left open. Rev.3.00 Jul. 19, 2007 page 12 of 532 REJ09B0397-0300 1. Overview Y 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 39 41 43 45 47 49 51 53 38 40 42 44 46 48 50 52 54 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Model (0, 0) X 55 56 57 58 59 61 63 65 67 69 71 60 62 64 66 68 70 72 Model: HD643385rccc r: Number denoting to ROM size 7: 60-kbyte version 6: 48-kbyte version 5: 40-kbyte version ccc: ROM code Chip size: 6.21 mm x 6.21 mm Figure 1.6 Pad Layout of HCD6433855, HCD6433856, and HCD6433857 (Mask ROM Version) (Top View) Rev.3.00 Jul. 19, 2007 page 13 of 532 REJ09B0397-0300 1. Overview Table 1.3 Pad No. Pad Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 P57 /WKP7 P56 /WKP6 P55 /WKP5 P54 /WKP4 P53 /WKP3 P52 /WKP2 P51 /WKP1 P50 /WKP0 P27 P26 P25 P24 P23 P22 P21 /UD HCD6433855, HCD6433856, and HCD6433857 Pad Coordinates Coordinates*1 X (m) Y (m) -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 2515 2365 2215 2070 1930 1795 1660 1530 1400 1271 1141 1011 881 751 621 491 290 125 -5 -135 -265 -395 -525 -655 -785 -960 -1169 -1299 -1428 -1581 -1734 -1874 -2024 -2189 -2384 Pad No. Pad Name 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 FWE*2 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9/SEG64 COM10/SEG63 COM11/SEG62 COM12/SEG61 COM13/SEG60 COM14/SEG59 COM15/SEG58 COM16/SEG57 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 Coordinates*1 X (m) Y (m) -2913 -2495 -2305 -2125 -1955 -1795 -1645 -1505 -1365 -1235 -1105 -975 -845 -715 -585 -455 -325 -195 -65 65 195 325 455 585 715 845 975 1105 1235 1365 1505 1645 1795 1955 2125 -2534 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 Pad No. Pad Name 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 COM32/SEG41 COM31/SEG42 COM30/SEG43 COM29/SEG44 COM28/SEG45 COM27/SEG46 COM26/SEG47 Coordinates*1 X (m) Y (m) 2305 2495 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 -2913 -2913 -2495 -2305 -2125 -1955 -1795 -1645 -1505 -1365 -1235 -1105 -975 -845 -715 -585 -455 -325 -195 -65 65 195 325 455 585 715 845 975 1105 1235 1365 1505 1645 1795 1955 P20 /IRQ4 /ADTRG -2913 AVCC PB0 /AN0 PB1 /AN1 PB2 /AN2 PB3 /AN3 PB4 /AN4 PB5 /AN5 PB6 /AN6 PB7 /AN7 AVSS X2 X1 VSS OSC2 OSC1 TEST TEST2 VCC RES -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 -2913 100 COM25/SEG48 101 COM24/SEG49 102 COM23/SEG50 103 COM22/SEG51 104 COM21/SEG52 105 COM20/SEG53 Rev.3.00 Jul. 19, 2007 page 14 of 532 REJ09B0397-0300 1. Overview Pad No. Pad Name 106 COM19/SEG54 107 COM18/SEG55 108 COM17/SEG56 109 V5OUT 110 V4OUT 111 V3OUT 112 V2OUT 113 V1OUT 114 V4 115 V34 116 V3 117 Vci 118 C2- Coordinates*1 X (m) Y (m) 2913 2913 2913 2435 2275 2125 1975 1825 1675 1520 1385 1255 1125 2125 2305 2495 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 Pad No. Pad Name 119 C2+ 120 C1- 121 C1+ 122 VLOUT 123 VLCD 124 VSS 125 P37 126 P36 127 P35 128 P34 129 P33 130 P32 /SO1 131 P31 /Sl1 Coordinates*1 X (m) Y (m) 995 865 735 605 475 325 195 65 -65 -195 -325 -455 -585 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 Pad No. Pad Name 132 P30 /SCK1 133 P17 /IRQ3/TMIF 134 P16 /IRQ2/TMIC 135 P15 /IRQ1/TMIB 136 P14 /PWM 137 P13 138 P12 /TMOFH 139 P11 /TMOFL 140 P10 /TMOW 141 P43 /IRQ0 142 P42 /TXD 143 P41 /RXD 144 P40 /SCK3 Coordinates*1 X (m) Y (m) -715 -845 -975 -1105 -1235 -1365 -1505 -1645 -1795 -1955 -2125 -2305 -2495 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 2913 Notes: 1. Numbers indicate coordinates at the center of the pad area, with an accuracy of 5 m. The origin is the center of the chip, and the center is at a point halfway between pads, horizontally and vertically. 2. Connect FWE to VSS. Rev.3.00 Jul. 19, 2007 page 15 of 532 REJ09B0397-0300 1. Overview Y 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 2-2 3 4 5 5-2 6 6-2 7 8 9 10 11 12 13 14 15 16 17 18 19-1 19-2 20 21 22 23 24 25 75 74 73 Model 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X (0, 0) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Model: HD64F3854 Chip size: 6.34 mm x 6.34 mm Figure 1.7 Pad Layout of HCD64F3854 (F-ZTAT Version) (Top View) Rev.3.00 Jul. 19, 2007 page 16 of 532 REJ09B0397-0300 1. Overview Table 1.4 Pad No. Pad Name 1 2 2-2 3 4 5 5-2 6 6-2 7 8 9 10 11 12 13 14 15 16 17 18 P56 /WKP6 P55 /WKP5 NC1*2 P54 /WKP4 P53 /WKP3 P52 /WKP2 NC2*2 P51 /WKP1 NC3*2 P50 /WKP0 P27 P26 P25 P24 P23 P22 P21 TEST2 X2 X1 HCD64F3854 Pad Coordinates Coordinates*1 X (m) Y (m) -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2448 -2244 -2040 -1836 -1617 2494 2333 2139 1950 1788 1626 1419 1215 1054 897 735 573 412 250 88 -73 -234 -396 -558 -716 -873 -1031 -1267 -1526 -1707 -1864 -2101 -2336 -2494 -2985 -2985 -2985 -2985 -2985 Pad No. Pad Name 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 Coordinates*1 X (m) Y (m) -1413 -1210 -1006 -801 -597 -393 -189 16 219 423 627 831 1035 1240 1443 1647 1851 2055 2259 2463 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2985 -2433 -2229 -2025 -1821 -1617 -1413 -1210 -1005 -801 -597 -393 -189 15 219 423 Pad No. Pad Name 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 V5OUT V4OUT V3OUT V2OUT V1OUT P17 /IRQ3 /TMIF P15 /IRQ1 /TMIB P12 /TMOFH P11 /TMOFL P10 /TMOW P43 /IRQ0 P42 /TXD P41 /RXD P40 /SCK3 Coordinates*1 X (m) Y (m) 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2435 2234 2032 1830 1629 1427 1226 1025 823 621 434 233 31 -171 -372 -574 -780 -985 -1191 -1396 -1618 -1820 -2022 -2234 -2446 627 831 1036 1240 1443 1647 1851 2055 2259 2463 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 2985 P20 /IRQ4 /ADTRG -2985 19-1 VSS*3 19-2 VSS*3 20 21 22 23 24 25 26 27 28 29 30 OSC2 OSC1 TEST VCC RES FWE PB4 /AN4 PB5 /AN5 PB6 /AN6 PB7 /AN7 COM1 100 P57 /WKP7 Notes: 1. Numbers indicate coordinates at the center of the pad area, with an accuracy of 5 m. The origin is the center of the chip, and the center is at a point halfway between pads, horizontally and vertically. 2. NC1 to NC3 are test pads; they should be left open. 3. Connect both 19-1 and 19-2 to VSS. Rev.3.00 Jul. 19, 2007 page 17 of 532 REJ09B0397-0300 1. Overview Y 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (0, 0) Model 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Model: HD643385rccc r: Number denoting to ROM size 4: 32-kbyte version 3: 24-kbyte version 2: 16-kbyte version ccc: ROM code Chip size: 4.69 mm x 4.69 mm Figure 1.8 Pad Layout of HCD6433854, HCD6433853, and HCD6433852 (Mask ROM Version) (Top View) Rev.3.00 Jul. 19, 2007 page 18 of 532 REJ09B0397-0300 1. Overview Table 1.5 Pad No. Pad Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 P56 /WKP6 P55 /WKP5 P54 /WKP4 P53 /WKP3 P52 /WKP2 P51 /WKP1 P50 /WKP0 P27 P26 P25 P24 P23 P22 P21 TEST2 X2 X1 VSS OSC2 OSC1 TEST VCC RES FWE*2 PB4 /AN4 PB5 /AN5 PB6 /AN6 PB7 /AN7 COM1 COM2 COM3 COM4 COM5 HCD6433852, HCD6433853, and HCD6433854 Pad Coordinates Coordinates*1 X (m) Y (m) -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -1722 -1552 -1395 -1236 -1060 -910 -780 -650 -520 1738 1590 1445 1305 1171 1041 911 781 651 521 391 261 131 1 -129 -259 -389 -519 -764 -1020 -1173 -1312 -1497 -1657 -1821 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 Pad No. Pad Name 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 Coordinates*1 X (m) Y (m) -390 -260 -130 0 130 260 390 520 650 780 910 1060 1213 1383 1551 1721 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -2161 -1721 -1551 -1383 -1213 -1060 -910 -780 -650 -520 -390 -260 -130 0 130 260 390 520 Pad No. Pad Name 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 V5OUT V4OUT V3OUT V2OUT V1OUT P17 /IRQ3 /TMIF P15 /IRQ1 /TMIB P12 /TMOFH P11 /TMOFL P10 /TMOW P43 /IRQ0 P42 /TXD P41 /RXD P40 /SCK3 Coordinates*1 X (m) Y (m) 2161 2161 2161 2161 2161 2161 2161 2161 1716 1565 1422 1282 1150 1020 890 760 630 500 197 67 -63 -193 -323 -453 -583 -713 -843 -973 -1104 -1244 -1383 -1534 -1698 650 780 910 1060 1213 1383 1551 1721 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 2161 P20 /IRQ4 /ADTRG -2161 100 P57 /WKP7 Notes: 1. Numbers indicate coordinates at the center of the pad area, with an accuracy of 5 m. The origin is the center of the chip, and the center is at a point halfway between pads, horizontally and vertically. 2. Connect FWE to VSS. Rev.3.00 Jul. 19, 2007 page 19 of 532 REJ09B0397-0300 1. Overview 1.3.2 Pin Functions Table 1.6 outlines the pin functions of the H8/3857 Group. Table 1.6 Pin Functions H8/3857 Group Pin No. Type Power source pins Symbol VCC FP-144H TFP-144 34 Pad No. 34 H8/3854 Group Pin No. FP-100B TFP-100G Pad No. 23 23 I/O Input Name and Functions Power supply: All VCC pins should be connected to the system power supply (+5 V) Ground: All VSS pins should be connected to the system power supply (0 V) Analog power supply (H8/3857 Group only): This is the power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). Analog ground (H8/3857 Group only): This is the A/D converter ground pin. It should be connected to the system power supply (0 V). This pin connects to a crystal or ceramic oscillator. See section 4, Clock Pulse Generators, for a typical connection diagram. This pin connects to a 32.768-kHz crystal oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram. VSS 29, 124 29, 124 19 19-1, 19-2 Input AVCC 17 17 Input AVSS 26 26 Input Clock pins OSC1 OSC2 31 30 31 30 21 20 21 20 Input Output X1 28 28 18 18 Input X2 27 27 17 17 Output Rev.3.00 Jul. 19, 2007 page 20 of 532 REJ09B0397-0300 1. Overview H8/3857 Group Pin No. Type System control Symbol RES FWE FP-144H TFP-144 35 36 Pad No. 35 36 H8/3854 Group Pin No. FP-100B TFP-100G Pad No. 24 25 24 25 I/O Input Input Name and Functions Reset: When this pin is driven low, the chip is reset Flash write enable: This pin enables or disables flash memory programming. In the mask ROM version, ground this pin to the VSS potential. Test: This is a test pin, not for use in application systems. It should be connected to VSS. Test pin: This pin sets the flash memory operating mode. In the mask ROM version, ground this pin to the VSS potential. External interrupt request 4 to 0 (H8/3857 Group) External interrupt request 4, 3, 1, 0 (H8/3854 Group) These are input pins for external interrupts for which there is a choice between rising and falling edge sensing. Input Wakeup interrupt request 0 to 7: These are input pins for external interrupts that are detected at the falling edge Clock output: This is an output pin for waveforms generated by the timer A output circuit Timer B event counter input: This is an event input pin for input to the timer B counter Timer C event counter input (H8/3857 Group only): This is an event input pin for input to the timer C counter TEST 32 32 22 22 Input TEST2 33 33 16 16 Input Interrupt pins IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 141 135 134 133 16 141 135 134 133 16 96 92 91 15 96 92 91 15 Input WKP7 to WKP0 1 to 8 1 to 8 100, 1 to 7 100, 1 to 7 Timer pins TMOW 140 140 95 95 Output TMIB 135 135 92 92 Input TMIC 134 134 Input Rev.3.00 Jul. 19, 2007 page 21 of 532 REJ09B0397-0300 1. Overview H8/3857 Group Pin No. Type Timer pins Symbol UD FP-144H TFP-144 15 Pad No. 15 H8/3854 Group Pin No. FP-100B TFP-100G Pad No. I/O Input Name and Functions Timer C up/down select (H8/3857 Group only): This pin selects whether the timer C counter is used for up- or down-counting. At high level it selects upcounting, and at low level down-counting. Timer F event counter input: This is an event input pin for input to the timer F counter Timer FL output: This is an output pin for waveforms generated by the timer FL output compare function Timer FH output: This is an output pin for waveforms generated by the timer FH output compare function 14-bit PWM output (H8/3857 Group only): This is an output pin for waveforms generated by the 14-bit PWM Port B: This is an 8-bit input port in the H8/3857 Group, and a 4-bit input port in the H8/3854 Group Port 4 (bit 3): This is a 1-bit input port Port 4 (bits 2 to 0): This is a 3-bit I/O port. Input or output can be designated for each bit by means of port control register 4 (PCR4). Port 1: This is an 8-bit I/O port in the H8/3857 Group, and a 5-bit I/O port in the H8/3854 Group. Input or output can be designated for each bit by means of port control register 1 (PCR1). TMIF 133 133 91 91 Input TMOFL 139 139 94 94 Output TMOFH 138 138 93 93 Output 14-bit PWM pin PWM 136 136 Output I/O ports PB7 to PB4 PB3 to PB0 25 to 22 21 to 18 25 to 22 21 to 18 29 to 26 29 to 26 Input P43 P42 to P40 141 141 96 97 to 99 96 97 to 99 Input I/O 142 to 144 142 to 144 P17, P16, P15, P14, P13, P12 to P10 133 134 135 136, 137 138 to 140 133 134 135 136, 137 138 to 140 91 92 93 to 95 91 92 93 to 95 I/O Rev.3.00 Jul. 19, 2007 page 22 of 532 REJ09B0397-0300 1. Overview H8/3857 Group Pin No. Type Symbol FP-144H TFP-144 9 to 16 Pad No. 9 to 16 H8/3854 Group Pin No. FP-100B TFP-100G Pad No. 8 to 15 8 to 15 I/O I/O Name and Functions Port 2: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 2 (PCR2). Port 3 (H8/3857 Group only): This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 3 (PCR3). Port 5: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 5 (PCR5). Port A: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA). PA2 to PA0 are connected internally to LCD pins RS, R/W, and STRB. Port 9: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 9 (PCR9). P97 to P90 are connected internally to LCD pins DB7 to DB0. SCI1 receive data input (H8/3857 Group only): This is the SCI1 data input pin SCI1 send data output (H8/3857 Group only): This is the SCI1 data output pin SCI1 clock I/O (H8/3857 Group only): This is the SCI1 clock I/O pin SCI3 receive data input: This is the SCI3 data input pin I/O ports P27 to P20 P37 to P30 125 to 132 125 to 132 I/O P57 to P50 1 to 8 1 to 8 100, 1 to 7 100, 1 to 7 I/O Internal PA3 to PA0 I/O ports I/O P97 to P90 I/O SI1 Serial communication interface SO1 (SCI) 131 131 Input 130 130 Output SCK1 132 132 I/O RXD 143 143 98 98 Input Rev.3.00 Jul. 19, 2007 page 23 of 532 REJ09B0397-0300 1. Overview H8/3857 Group Pin No. Type Symbol FP-144H TFP-144 142 Pad No. 142 H8/3854 Group Pin No. FP-100B TFP-100G Pad No. 97 97 I/O Output Name and Functions SCI3 send data output: This is the SCI3 data output pin SCI3 clock I/O : This is the SCI3 clock I/O pin Analog input (channels 7 to 0 in H8/3857 Group, channels 7 to 4 in H8/3854 Group): These are analog data input channels to the A/D converter A/D converter trigger input: This is the external trigger input pin to the A/D converter LCD common output: These are LCD common output pins. The maximum number of pins is 32 in the H8/3857 Group, and 16 in the H8/3854 Group. In standby mode and module standby mode, all pins output the VSS level. LCD segment output: These are LCD segment output pins. The maximum number of pins is 64 in the H8/3857 Group, and 40 in the H8/3854 Group. In standby mode and module standby mode, all pins output the VSS level. LCD bias setting pins (H8/3857 Group only): 1/4 bias drive is selected when V3 and V4 are shorted, and 1/5 bias drive when V3 and V4 are left open. LCD test pin (H8/3857 Group only): This is the LCD built-in resistance test pin. V3 and V34 must be shorted. Serial TXD communication interface SCK3 (SCI) 144 144 25 to 22 21 to 18 99 29 to 26 99 29 to 26 I/O Input A/D AN7 to AN4 25 to 22 converter AN3 to AN0 21 to 18 ADTRG 16 16 15 15 Input LCD COM32 to controller COM17 COM16 to COM1 93 to 108 52 to 37 93 to 108 52 to 37 45 to 30 45 to 30 Output SEG64 to SEG41 SEG40 to SEG1 45 to 52 108 to 93, 92 to 53 45 to 52 108 to 93, 92 to 53 85 to 46 85 to 46 Output V3, V4 116, 114 116, 114 Input V34 115 115 Input Rev.3.00 Jul. 19, 2007 page 24 of 532 REJ09B0397-0300 1. Overview H8/3857 Group Pin No. Type Symbol FP-144H TFP-144 Pad No. H8/3854 Group Pin No. FP-100B TFP-100G Pad No. I/O Name and Functions LCD step-up circuit capacitance connection pins (H8/3857 Group only): These pins connect external capacitances for LCD step-up. Connect capacitances according to the step-up factor. LCD drive power supply level (H8/3857 Group): When the OPON bit is set high, these bits output LCD drive power supply levels V1 to V5. If the built-in op-amp drive capacity is inadequate, connect a capacitor to provide stabilization. If levels V1 to V5 are input from an external source, set the OPON bit low. LCD step-up circuit reference power supply (H8/3857 Group only): This pin doubles as the LCD step-up circuit reference input voltage and step-up circuit power supply, and provides the LCD drive voltage. Set 1.6 V Vci VCC. If the step-up circuit is not used, connect Vci to VCC. LCD step-up voltage output (H8/3857 Group only): This is the LCD stepup voltage output pin. Connect a capacitance. LCD drive power supply (H8/3857 Group only): This is the LCD drive power supply input pin. If the builtin step-up circuit output voltage is used for the LCD drive power supply, short this pin to VLOUT. Set VCC VLCD 7.0 V. LCD C1+, C1-, controller C2+, C2- 121 to 118 121 to 118 H8/3857 V1OUT to V5OUT Group LCD power supply 113 to 109 113 to 109 I/O Vci 117 117 Input VLOUT 122 122 Output VLCD 123 123 Input Rev.3.00 Jul. 19, 2007 page 25 of 532 REJ09B0397-0300 1. Overview H8/3857 Group Pin No. Type Symbol FP-144H TFP-144 Pad No. H8/3854 Group Pin No. FP-100B TFP-100G Pad No. 90 to 86 90 to 86 I/O I/O Name and Functions LCD drive power supply level (H8/3854 Group): When the LPS1 and LPS0 bits are set high, these pins output LCD drive power supply levels V1 to V5. If the drive capacity is inadequate, connect a capacitor to provide stabilization. If levels V1 to V5 are input from an external source, set the LPS1 and LPS0 bits low. The V1 to V5 levels must not exceed VCC. When driving with a 1/4 bias, short V3OUT and V4OUT. H8/3854 V1OUT to V5OUT Group LCD power supply Rev.3.00 Jul. 19, 2007 page 26 of 532 REJ09B0397-0300 2. CPU Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. * General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit general registers * Instruction set with 55 basic instructions, including: Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment or pre-decrement Absolute address Immediate Program-counter relative Memory indirect * 64-kbyte address space * High-speed operation All frequently used instructions are executed in two to four states High-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.4 s* 8 x 8-bit multiply: 2.8 s* 16 / 8-bit divide: 2.8 s* Note: * These values are at = 5 MHz. * Low-power operation modes SLEEP instruction for transfer to low-power operation Rev.3.00 Jul. 19, 2007 page 27 of 532 REJ09B0397-0300 2. CPU 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack Pointer 0 Control registers (CR) 15 PC 76543210 I UHUNZVC 0 PC: Program Counter CCR: Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit CCR Figure 2.1 CPU Registers Rev.3.00 Jul. 19, 2007 page 28 of 532 REJ09B0397-0300 2. CPU 2.2 2.2.1 Register Descriptions General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7) points to the top of the stack. Lower address side [H'0000] Unused area SP (R7) Stack area Upper address side [H'FFFF] Figure 2.2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0). Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, Rev.3.00 Jul. 19, 2007 page 29 of 532 REJ09B0397-0300 2. CPU ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see section 3.3, Interrupts. Bit 6--User Bit (U): Can be used freely by the user. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4--User Bit (U): Can be used freely by the user. Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when operation execution generates a carry, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. Refer to the H8/300L Series Software Manual for the action of each instruction on the flag bits. Rev.3.00 Jul. 19, 2007 page 30 of 532 REJ09B0397-0300 2. CPU 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 Data Formats The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). * All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. * The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. * The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. Rev.3.00 Jul. 19, 2007 page 31 of 532 REJ09B0397-0300 2. CPU 2.3.1 Data Formats in General Registers The general register data formats are shown in figure 2.3. Data Type Register No. 7 Data Format 0 1-bit data RnH 7 6 5 4 3 2 1 0 don't care 7 0 1-bit data RnL don't care 7 6 5 4 3 2 1 0 7 0 LSB Byte data RnH MSB don't care 7 0 LSB Byte data RnL don't care MSB 15 0 LSB Word data Rn MSB 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnH don't care 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnL don't care Legend: RnH: Upper byte of general register RnL: Lower byte of general register MSB: Most significant bit LSB: Least significant bit Figure 2.3 Register Data Formats Rev.3.00 Jul. 19, 2007 page 32 of 532 REJ09B0397-0300 2. CPU 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address. This rule affects the MOV.W instruction, and also applies to instruction fetching. Data Type Address Data Format 7 0 1-bit data Byte data Address n Address n Even address Odd address Even address Odd address Even address Odd address 7 MSB 6 5 4 3 2 1 0 LSB Word data MSB Upper 8 bits Lower 8 bits LSB Byte data (CCR) on stack MSB MSB CCR CCR* LSB LSB Word data on stack MSB LSB Legend: CCR: Condition code register Note: * Ignored on return Figure 2.4 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. For the CCR, the same value is stored in the upper 8 bits and lower 8 bits as word data. On return, the lower 8 bits are ignored. Rev.3.00 Jul. 19, 2007 page 33 of 532 REJ09B0397-0300 2. CPU 2.4 2.4.1 Addressing Modes Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 No. 1 2 3 4 5 6 7 8 Addressing Modes Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8 1. Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. 2. Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. Register Indirect with Displacement--@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a 16-bit displacement which is added to the contents of the specified general register (16-bit) to obtain the operand address in memory. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even. Rev.3.00 Jul. 19, 2007 page 34 of 532 REJ09B0397-0300 2. CPU 4. Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with post-increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. * Register indirect with pre-decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even. 5. Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535). 6. Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. Program-Counter Relative--@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. The displacement should be an even number. Rev.3.00 Jul. 19, 2007 page 35 of 532 REJ09B0397-0300 2. CPU 8. Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See section 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.3.2, Memory Data Formats, for further information. 2.4.2 Effective Address Calculation Table 2.2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (8bit) (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position. Rev.3.00 Jul. 19, 2007 page 36 of 532 REJ09B0397-0300 2. CPU Table 2.2 No. 1 Effective Address Calculation Effective Address Calculation Method Effective Address (EA) 3 0 3 0 Addressing Mode and Instruction Format Register direct, Rn 15 87 43 0 rm op rm rn rn Operand is contents of registers indicated by rm/rn 15 Contents (16 bits) of register indicated by rm 0 15 0 2 Register indirect, @Rn 15 76 43 0 op rm 15 Contents (16 bits) of register indicated by rm 0 15 0 3 Register indirect with displacement, @(d:16, Rn) 15 76 43 0 op disp rm disp 4 Register indirect with post-increment, @Rn+ 15 76 43 0 15 Contents (16 bits) of register indicated by rm 0 15 0 op rm 1 or 2 Register indirect with pre-decrement, @-Rn 15 76 43 0 15 Contents (16 bits) of register indicated by rm 0 15 0 op rm Incremented or decremented by 1 if operand is byte size, 1 or 2 and by 2 if word size Rev.3.00 Jul. 19, 2007 page 37 of 532 REJ09B0397-0300 2. CPU Addressing Mode and Instruction Format Absolute address @aa:8 15 87 0 No. 5 Effective Address Calculation Method Effective Address (EA) 15 87 0 H'FF op @aa:16 15 abs 0 15 0 op abs 6 Immediate #xx:8 15 87 0 op #xx:16 15 IMM Operand is 1- or 2-byte immediate data 0 op IMM 7 Program-counter relative @(d:8, PC) 15 0 PC contents 15 0 15 87 0 Sign extension disp op disp Rev.3.00 Jul. 19, 2007 page 38 of 532 REJ09B0397-0300 2. CPU Addressing Mode and Instruction Format Memory indirect, @@aa:8 15 87 0 No. 8 Effective Address Calculation Method Effective Address (EA) op abs 15 87 0 H'00 abs 15 0 Memory contents (16 bits) Legend: rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Rev.3.00 Jul. 19, 2007 page 39 of 532 REJ09B0397-0300 2. CPU 2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer Instruction Set Instructions MOV, PUSH* , POP* 1 1 Number 1 14 4 8 14 5 8 1 Total: 55 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. The machine language is also the same. 2. Bcc is the generic term for conditional branch instructions. The functions of the instructions are shown in tables 2.4 to 2.11. The meaning of the operation symbols used in the tables is as follows. Rev.3.00 Jul. 19, 2007 page 40 of 532 REJ09B0397-0300 2. CPU Operation Notation Rd Rs Rn (EAd), Rev.3.00 Jul. 19, 2007 page 41 of 532 REJ09B0397-0300 2. CPU 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Instruction MOV Data Transfer Instructions Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. POP W @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. PUSH W Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. Note: * Size: Operand size B: Byte W: Word Certain precautions are required in data access. See section 2.9.1, Notes on Data Access, for details. Rev.3.00 Jul. 19, 2007 page 42 of 532 REJ09B0397-0300 2. CPU 15 8 7 0 MOV RmRn op 15 8 7 rm rn 0 op 15 8 7 rm rn 0 @RmRn op disp 15 8 7 rm rn @(d:16, Rm)Rn 0 op 15 8 7 rm rn 0 @Rm+Rn, or Rn @-Rm op 15 rn 8 7 abs 0 @aa:8Rn op abs 15 8 7 rn @aa:16Rn 0 op 15 rn 8 7 IMM 0 #xx:8Rn op IMM 15 8 7 rn #xx:16Rn 0 op Legend: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data 1 1 1 rn PUSH, POP @SP+ Rn, or Rn @-SP Figure 2.5 Data Transfer Instruction Codes Rev.3.00 Jul. 19, 2007 page 43 of 532 REJ09B0397-0300 2. CPU 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Instruction ADD SUB Arithmetic Instructions Size* B/W Function Rd Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. B W Rd 1 Rd Increments or decrements a general register by 1. Rd 1 Rd, Rd 2 Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. B Rd decimal adjust Rd Decimal-adjusts (adjusts to packed 4-bit BCD) an addition or subtraction result in a general register by referring to the CCR B Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU DIVXU B Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder CMP B/W Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and the result is stored in the CCR. Word data can be compared only between two general registers. NEG B 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register Note: * Size: Operand size B: Byte W: Word Rev.3.00 Jul. 19, 2007 page 44 of 532 REJ09B0397-0300 2. CPU 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Instruction AND Logic Operation Instructions Size* B Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data OR B Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B ~ Rd Rd Obtains the one's complement (logical complement) of general register contents Note: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2.7 describes the eight shift instructions. Table 2.7 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * B B B Shift Instructions Size* B Function Rd shift Rd Performs an arithmetic shift operation on general register contents Rd shift Rd Performs a logical shift operation on general register contents Rd rotate Rd Rotates general register contents Rd rotate Rd Rotates general register contents through the carry flag. Size: Operand size B: Byte Rev.3.00 Jul. 19, 2007 page 45 of 532 REJ09B0397-0300 2. CPU Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 8 7 0 op 15 8 7 rm rn 0 ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT 0 op 15 8 7 rn op 15 8 7 rm rn 0 MULXU, DIVXU op 15 rn 8 7 IMM 0 ADD, ADDX, SUBX, CMP (#XX:8) op 15 8 7 rm rn 0 AND, OR, XOR (Rm) op 15 rn 8 7 IMM 0 AND, OR, XOR (#xx:8) op Legend: op: Operation field rm, rn: Register field IMM: Immediate data rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes Rev.3.00 Jul. 19, 2007 page 46 of 532 REJ09B0397-0300 2. CPU 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Instruction BSET Bit-Manipulation Instructions Size* B Function 1 ( BCLR B 0 ( BNOT B ~ ( BTST B ~ ( BAND B C ( BIAND B C [~ ( BOR B C ( BIOR B C [~ ( Note: * Size: Operand size B: Byte Rev.3.00 Jul. 19, 2007 page 47 of 532 REJ09B0397-0300 2. CPU Instruction BXOR Size* B Function C ( Certain precautions are required in bit manipulation. See section 2.9.2, Notes on Bit Manipulation, for details. Rev.3.00 Jul. 19, 2007 page 48 of 532 REJ09B0397-0300 2. CPU BSET, BCLR, BNOT, BTST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) 0 op 15 8 7 rm rn op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op 15 8 7 rn rm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 register direct (Rm) op op 15 8 7 abs IMM 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: 0 immediate (#xx:3) op op rm abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (1) Rev.3.00 Jul. 19, 2007 page 49 of 532 REJ09B0397-0300 2. CPU BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (2) Rev.3.00 Jul. 19, 2007 page 50 of 532 REJ09B0397-0300 2. CPU 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Instruction Bcc Branching Instructions Size Function Branches to the designated address if the specified condition is true. The branching conditions are given below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine Rev.3.00 Jul. 19, 2007 page 51 of 532 REJ09B0397-0300 2. CPU 15 8 7 0 op 15 cc 8 7 disp 0 Bcc op 15 8 7 rm 0 0 0 0 0 JMP (@Rm) op abs 15 8 7 0 JMP (@aa:16) op 15 8 7 abs 0 JMP (@@aa:8) op 15 8 7 disp 0 BSR op 15 8 7 rm 0 0 0 0 0 JSR (@Rm) op abs 15 8 7 0 JSR (@aa:16) op 15 8 7 abs 0 JSR (@@aa:8) op Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address RTS Figure 2.8 Branching Instruction Codes Rev.3.00 Jul. 19, 2007 page 52 of 532 REJ09B0397-0300 2. CPU 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction RTE SLEEP LDC Size* B Function Returns from an exception-handling routine Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details Rs CCR, #IMM CCR Moves immediate data or general register contents to the condition code register STC ANDC ORC XORC NOP Note: * B B B B CCR Rd Copies the condition code register to a specified general register CCR #IMM CCR Logically ANDs the condition code register with immediate data CCR #IMM CCR Logically ORs the condition code register with immediate data CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data PC + 2 PC Only increments the program counter Size: Operand size B: Byte Rev.3.00 Jul. 19, 2007 page 53 of 532 REJ09B0397-0300 2. CPU 15 8 7 0 op 15 8 7 0 RTE, SLEEP, NOP op 15 8 7 rn 0 LDC, STC (Rn) op Legend: op: Operation field rn: Register field IMM: Immediate data IMM ANDC, ORC, XORC, LDC (#xx:8) Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction EEPMOV Size Function if R4L 0 then repeat until else next; Block transfer instruction. Transfers the number of bytes specified by R4L, from locations starting at the address specified by R5, to locations starting at the address specified by R6. On completion of the transfer, the next instruction is executed. @R5+ @R6+ R4L - 1 R4L R4L = 0 Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, Notes on Use of the EEPMOV Instruction, for details. Rev.3.00 Jul. 19, 2007 page 54 of 532 REJ09B0397-0300 2. CPU 15 8 7 0 op op Legend: op: Operation field Figure 2.10 Block Data Transfer Instruction Code 2.6 Basic Operational Timing CPU operation is synchronized by a system clock () or a subclock (SUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.11 shows the on-chip memory access cycle. Bus cycle T1 state or SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.11 On-Chip Memory Access Cycle Rev.3.00 Jul. 19, 2007 page 55 of 532 REJ09B0397-0300 2. CPU 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Figures 2.12 and 2.13 show the on-chip peripheral module access cycle. Two-State Access to On-Chip Peripheral Modules Bus cycle T1 state or SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access) Rev.3.00 Jul. 19, 2007 page 56 of 532 REJ09B0397-0300 2. CPU Three-State Access to On-Chip Peripheral Modules Bus cycle T1 state or SUB T2 state T3 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Address Read data Write data Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) 2.7 2.7.1 CPU States Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2.14. Figure 2.15 shows the state transitions. Rev.3.00 Jul. 19, 2007 page 57 of 532 REJ09B0397-0300 2. CPU CPU state Reset state The CPU is initialized. Program execution state Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Low-power modes Program halt state A state in which some or all of the chip functions are stopped to conserve power Sleep mode Standby mode Watch mode Subsleep mode Exceptionhandling state A transient state entered when the CPU changes the processing flow due to a reset or interrupt exception handling source. Note: See section 5, Power-Down Modes, for details on the modes and their transitions. Figure 2.14 CPU Operation States Rev.3.00 Jul. 19, 2007 page 58 of 532 REJ09B0397-0300 2. CPU Reset cleared Reset state Reset occurs Exception-handling state Reset occurs Reset occurs Interrupt source Interrupt source Exceptionhandling complete Program halt state SLEEP instruction executed Program execution state Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. Operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for details on these modes. 2.7.3 Program Halt State In the program halt state there are four modes: sleep mode, standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on these modes. 2.7.4 Exception-Handling State The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack. For details on interrupt handling, see section 3.3 Interrupts. Rev.3.00 Jul. 19, 2007 page 59 of 532 REJ09B0397-0300 2. CPU 2.8 2.8.1 Memory Map Memory Map The memory maps of the H8/3857 Group and H8/3854 Group are shown in figures 2.16 (a) and (b). H8/3855 H8/3856 H8/3857 H8/3857F H'0000 H'0029 H'002A Interrupt vector (42 bytes) On-chip ROM 40 kbytes 48 kbytes 60 kbytes 60 kbytes H'9FFF H'BFFF H'EDFF Not used H'F77F H'F780 On-chip RAM 2,048 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16 (a) H8/3857 Group Memory Map Rev.3.00 Jul. 19, 2007 page 60 of 532 REJ09B0397-0300 2. CPU H8/3854*1 H8/3854F*1 H8/3852 H'0000 H'0029 H'002A Interrupt vector (42 bytes) 16 kbytes On-chip ROM H'3FFF H8/3853 24 kbytes 32 kbytes 60 kbytes H'5FFF H'7FFF H'EDFF Not used H'F77F H'F780 On-chip RAM H'FB7F H'FB80 H8/3852 H8/3853 H8/3854 1,024 bytes*2 H8/3854F 2,048 bytes*2 H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Notes: 1. Note that the H8/3854 (mask ROM version) and H8/3854F (F-ZTAT version) have different ROM and RAM sizes. 2. The start address for 2-kbyte RAM is H'F780, and the start address for 1-kbyte RAM is H'FB80. Figure 2.16 (b) H8/3854 Group Memory Map Rev.3.00 Jul. 19, 2007 page 61 of 532 REJ09B0397-0300 2. CPU 2.9 2.9.1 Application Notes Notes on Data Access Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. * Data transfer from CPU to empty area The transferred data will be lost. This action may also cause the CPU to misoperate. * Data transfer from empty area to CPU Unpredictable data is transferred. Access to Internal I/O Registers: Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. * Word access from CPU to I/O register area Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. * Word access from I/O register to CPU Upper byte: Will be written to upper part of CPU register. Lower byte: Unpredictable data will be written to lower part of CPU register. Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas. Figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed. Rev.3.00 Jul. 19, 2007 page 62 of 532 REJ09B0397-0300 2. CPU Access States Word H'0000 H'0029 H'002A 60 kbytes*1 On-chip ROM 2 Interrupt vector area (42 bytes) Byte *1 H'EDFF Not used -- -- -- H'F780 On-chip RAM H'FF7F H'FF80 2 Internal I/O registers (128 bytes) H'FFA8 H'FFAD H'FFFF 3 2 2048 bytes*2 2 Notes: The above example is a description of the H8/3857, H8/3857F, and H8/3854F. 1. The H8/3855 has 40 kbytes of on-chip ROM, ending at address H'9FFF, the H8/3856 has 48 kbytes, ending at address H'BFFF, the H8/3852 has 16 kbytes, ending at address H'3FFF, the H8/3853 has 24 kbytes, ending at address H'5FFF, and the H8/3854 (mask ROM version) has 32 kbytes, ending at address H'7FFF. 2. The H8/3857 Group and the H8/3854F have 2,048 bytes of on-chip RAM, and the H8/3854 Group (mask ROM version) has 1,024 bytes, starting at address H'FB80. Figure 2.17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules Rev.3.00 Jul. 19, 2007 page 63 of 532 REJ09B0397-0300 2. CPU 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O. Order of Operation 1 2 3 Read Modify Write Operation Read byte data at the designated address Modify a designated bit in the read data Write the altered byte data to the designated address Bit Manipulation in Two Registers Assigned to the Same Address Example 1: Timer load register and timer count bit manipulation Figure 2.18 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. Order of Operation 1 2 3 Read Modify Write Operation Timer counter data is read (one byte) The CPU modifies (sets or resets) the bit designated in the instruction The altered byte data is written to the timer load register The timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. R Count clock Timer counter Reload W Timer load register Legend: R: Read W: Write Internal bus Figure 2.18 Timer Configuration Example Rev.3.00 Jul. 19, 2007 page 64 of 532 REJ09B0397-0300 2. CPU Example 2: When a BSET instruction is executed on port 3 P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P30 to high-level output. [A: Prior to executing BSET] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0 [B: BSET instruction executed] BSET #0 , @PDR3 The BSET instruction is executed designating port 3. [C: After executing BSET] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 0 P36 Input High level 0 1 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output High level 1 1 [D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 3. Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input). P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value of H'80, but the value read by the CPU is H'40. Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU writes this value (H'41) to PDR3, completing execution of BSET. Rev.3.00 Jul. 19, 2007 page 65 of 532 REJ09B0397-0300 2. CPU As a result of this operation, bit 0 in PDR3 becomes 1, and P30 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] MOV. B MOV. B MOV. B #80, R0L, R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 R0L @RAM0 @PDR3 P36 Input High level 0 0 0 The PDR3 value (H'80) is written to a work area in memory (RAM0) as well as to PDR3. P35 Output Low level 1 0 0 P34 Output Low level 1 0 0 P33 Output Low level 1 0 0 P32 Output Low level 1 0 0 P31 Output Low level 1 0 0 P30 Output Low level 1 0 0 [B: BSET instruction executed] BSET #0 , @RAM0 The BSET instruction is executed designating the PDR3 work area (RAM0). [C: After executing BSET] MOV. B MOV. B @RAM0, R0L R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 The work area (RAM0) value is written to PDR3. @PDR3 P36 Input High level 0 0 0 P35 Output Low level 1 0 0 P34 Output Low level 1 0 0 P33 Output Low level 1 0 0 P32 Output Low level 1 0 0 P31 Output Low level 1 0 0 P30 Output High level 1 1 1 Rev.3.00 Jul. 19, 2007 page 66 of 532 REJ09B0397-0300 2. CPU Bit Manipulation in a Register Containing a Write-Only Bit Example 3: When a BCLR instruction is executed on PCR3 of port 3 As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is assumed that a high-level signal will be input to this input pin. [A: Prior to executing BCLR] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0 [B: BCLR instruction executed] BCLR #0 , @PCR3 The BCLR instruction is executed designating PCR3. [C: After executing BCLR] P37 Input/output Pin state PCR3 PDR3 Output Low level 1 1 P36 Output High level 1 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Input High level 0 0 [D: Explanation of how BCLR operates] When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value (H'FE) is written to PCR3 and BCLR instruction execution ends. Rev.3.00 Jul. 19, 2007 page 67 of 532 REJ09B0397-0300 2. CPU As a result of this operation, bit 0 in PCR3 becomes 0, making P30 an input port. However, bits 7 and 6 in PCR3 change to 1, so that P37 and P36 change from input pins to output pins. To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] MOV. B MOV. B MOV. B #3F, R0L, R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 R0L @RAM0 @PCR3 P36 Input High level 0 0 0 The PCR3 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR3. P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output Low level 1 0 1 [B: BCLR instruction executed] BCLR #0 , @RAM0 The BCLR instruction is executed designating the PCR3 work area (RAM0). [C: After executing BCLR] MOV. B MOV. B @RAM0, R0L R0L, @PCR3 P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 P36 Input High level 0 0 0 The work area (RAM0) value is written to PCR3. P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output High level 0 0 0 Rev.3.00 Jul. 19, 2007 page 68 of 532 REJ09B0397-0300 2. CPU Table 2.12 lists registers that share the same address, and table 2.13 lists registers that contain write-only bits. Table 2.12 Registers with shared addresses Register Name Timer counter B and timer load register B Timer counter C and timer load register C* Port data register 1* * Port data register 2*1 Port data register 3* * Port data register 4* Port data register 5* Port data register 9* 1 1 1 2 1 3 2 Abbreviation TCB/TLB TCC/TLC PDR1 PDR2 PDR3 PDR4 PDR5 PDR9 PDRA Address H'FFB3 H'FFB5 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFDC H'FFDD 1 Port data register A* 1 Notes: 1. These port registers are used also for pin input. 2. A function of the H8/3857 Group only; not provided in the H8/3854 Group. 3. Some bits are not present in the H8/3854 Group. Table 2.13 Registers with write-only bits Register Name Port control register 1* Port control register 2 Port control register 3* Port control register 4 Port control register 5 Port control register 9 Port control register A Timer control register F PWM control register*2 PWM data register U* PWM data register L* 2 2 2 1 Abbreviation PCR1 PCR2 PCR3 PCR4 PCR5 PCR9 PCRA TCRF PWCR PWDRU PWDRL Address H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFEC H'FFED H'FFB6 H'FFD0 H'FFD1 H'FFD2 Notes: 1. Some bits are not present in the H8/3854 Group. 2. A function of the H8/3857 Group only; not provided in the H8/3854 Group. Rev.3.00 Jul. 19, 2007 page 69 of 532 REJ09B0397-0300 2. CPU 2.9.3 Notes on Use of the EEPMOV Instruction * The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 R6 R5 + R4L R6 + R4L * When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 R6 R5 + R4L H'FFFF Not allowed R6 + R4L Rev.3.00 Jul. 19, 2007 page 70 of 532 REJ09B0397-0300 3. Exception Handling Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3857 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Priority High Exception Handling Types and Priorities Exception Source Reset Interrupt Time of Start of Exception Handling Exception handling starts as soon as the reset state is cleared When an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed Low 3.2 3.2.1 Reset Overview A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized. 3.2.2 Reset Sequence As soon as the RES pin goes low, all processing is stopped and the H8/3857 enters the reset state. To make sure the chip is reset properly, observe the following precautions. * At power on: Hold the RES pin low until the clock pulse generator output stabilizes. * Resetting during operation: Hold the RES pin low for at least 10 system clock cycles. When the RES pin goes high again after being held low for a given period, reset exception handling begins. Reset exception handling takes place as follows: * The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. * The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC. When system power is turned on or off, the RES pin should be held low. Rev.3.00 Jul. 19, 2007 page 71 of 532 REJ09B0397-0300 3. Exception Handling Figure 3.1 shows the reset sequence. Reset cleared Program initial instruction prefetch Vector fetch Internal processing RES Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) (1) (2) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3.1 Reset Sequence 3.2.3 Interrupt Immediately after Reset After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP). Rev.3.00 Jul. 19, 2007 page 72 of 532 REJ09B0397-0300 3. Exception Handling 3.3 3.3.1 Interrupts Overview In the H8/3857 Group, sources that initiate interrupt exception handling include 13 external interrupts (WKP7 to WKP0, and IRQ4 to IRQ0), and 16 internal interrupts from on-chip peripheral modules. In the H8/3854 Group, sources that initiate interrupt exception handling include 12 external interrupts (WKP7 to WKP0, IRQ4, IRQ3, IRQ1, and IRQ0), and 14 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed. The interrupts have the following features: * Both internal and external interrupts can be masked by the I bit of CCR. When this bit is set to 1, interrupt request flags are set but interrupts are not accepted. * The external interrupt pins IRQ0 to IRQ4 can each be set independently to either rising edge sensing or falling edge sensing. Rev.3.00 Jul. 19, 2007 page 73 of 532 REJ09B0397-0300 3. Exception Handling Table 3.2 Priority High Interrupt Sources and Priorities Interrupt Source RES IRQ0 IRQ1 IRQ2* IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 SCI1* 2 2 Interrupt Reset IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 SCI1 transfer complete Timer A overflow Timer B overflow Timer C overflow or underflow Timer FL compare match Timer FL overflow Timer FH compare match Timer FH overflow SCI3 transmit end SCI3 transmit data empty SCI3 receive data full SCI3 overrun error SCI3 framing error SCI3 parity error Vector Number 0 4 5 6 7 8 9 Vector Address*1 H'0000 to H'0001 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 10 11 12 13 14 15 18 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0024 to H'0025 Timer A Timer B Timer C*2 Timer FL Timer FH SCI3 A/D converter Low (SLEEP instruction executed) A/D conversion end Direct transfer 19 20 H'0026 to H'0027 H'0028 to H'0029 Notes: 1. Vector addresses H'0002 to H'0007 and H'0020 to H'0023 are reserved and cannot be used. 2. Applies to the H8/3857 Group. In the H8/3854 Group, these vector addresses are reserved. Rev.3.00 Jul. 19, 2007 page 74 of 532 REJ09B0397-0300 3. Exception Handling 3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Abbreviation 2 Register Name IRQ edge select register* 2 R/W R/W R/W R/W R/W*1 R/W*1 R/W* 1 Initial Value H'E0 H'00 H'00 H'20 H'00 H'00 Address H'FFF2 H'FFF3 H'FFF4 H'FFF6 H'FFF7 H'FFF9 IEGR IENR1 IENR2 IRR1 IRR2 IWPR 2 Interrupt enable register 1* Interrupt enable register 2* Interrupt request register 1*2 Interrupt request register 2*2 Wakeup interrupt request register Notes: 1. Write is enabled only for writing of 0 to clear a flag. 2. There are some differences in functions between the H8/3857 Group and the H8/3854 Group. For details, see the individual register descriptions. IRQ Edge Select Register (IEGR) Bit 7 Initial value Read/Write Note: * 1 6 1 5 1 4 IEG4 0 R/W 3 IEG3 0 R/W 2 IEG2* 0 R/W 1 IEG1 0 R/W 0 IEG0 0 R/W Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to 0. IEGR is an 8-bit read/write register, used to designate whether pins IRQ0 to IRQ4 are set to rising edge sensing or falling edge sensing. Bits 7 to 5--Reserved Bits: Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4--IRQ4 Edge Select (IEG4): Bit 4 selects the input sensing of pin IRQ4/ADTRG. Bit 4: IEG4 0 1 Description Falling edge of IRQ4/ADTRG pin input is detected Rising edge of IRQ4/ADTRG pin input is detected (initial value) Rev.3.00 Jul. 19, 2007 page 75 of 532 REJ09B0397-0300 3. Exception Handling Bit 3--IRQ3 Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ3/TMIF. Bit 3: IEG3 0 1 Description Falling edge of IRQ3/TMIF pin input is detected Rising edge of IRQ3/TMIF pin input is detected (initial value) Bit 2--IRQ2 Edge Select (IEG2): Bit 2 is used in the H8/3857 Group to select the input sensing of pin IRQ2/TMIC. In the H8/3854 Group, this bit must always be cleared to 0. Bit 2: IEG2 0 1 Description Falling edge of IRQ2/TMIC pin input is detected Rising edge of IRQ2/TMIC pin input is detected (initial value) Bit 1--IRQ1 Edge Select (IEG1): Bit 1 selects the input sensing of pin IRQ1/TMIB. Bit 1: IEG1 0 1 Description Falling edge of IRQ1/TMIB pin input is detected Rising edge of IRQ1/TMIB pin input is detected (initial value) Bit 0--IRQ0 Edge Select (IEG0): Bit 0 selects the input sensing of pin IRQ0. Bit 0: IEG0 0 1 Description Falling edge of IRQ0 pin input is detected Rising edge of IRQ0 pin input is detected (initial value) Interrupt Enable Register 1 (IENR1) Bit 7 IENTA Initial value Read/Write Note: * 0 R/W 6 IENS1* 0 R/W 5 IENWP 0 R/W 4 IEN4 0 R/W 3 IEN3 0 R/W 2 IEN2* 0 R/W 1 IEN1 0 R/W 0 IEN0 0 R/W Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to 0. IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Rev.3.00 Jul. 19, 2007 page 76 of 532 REJ09B0397-0300 3. Exception Handling Bit 7--Timer A Interrupt Enable (IENTA): Bit 7 enables or disables timer A overflow interrupt requests. Bit 7: IENTA 0 1 Description Disables timer A interrupts Enables timer A interrupts (initial value) Bit 6--SCI1 Interrupt Enable (IENS1): Bit 6 is used in the H8/3857 Group to enable or disable SCI1 transfer complete interrupt requests. In the H8/3854 Group, this bit must always be cleared to 0. Bit 6: IENS1 0 1 Description Disables SCI1 interrupts Enables SCI1 interrupts (initial value) Bit 5--Wakeup Interrupt Enable (IENWP): Bit 5 enables or disables WKP7 to WKP0 interrupt requests. Bit 5: IENWP 0 1 Description Disables interrupt requests from WKP7 to WKP0 Enables interrupt requests from WKP7 to WKP0 (initial value) Bits 4, 3, 1, and 0--IRQ4, IRQ3, IRQ1, and IRQ0 Interrupt Enable (IEN4, IEN3, IEN1, IEN0): Bits 4 to 0 enable or disable IRQ4, IRQ3, IRQ1, and IRQ0 interrupt requests. Bit n: IENn 0 1 Description Disables interrupt request IRQn Enables interrupt request IRQn (initial value) Note: n = 4, 3, 1, or 0 Bit 2--IRQ2 Interrupt Enable (IEN2): Bit 2 is used in the H8/3857 Group to enable or disable IRQ2 interrupt requests. In the H8/3854 Group, this bit must always be cleared to 0. Bit 2: IEN2 0 1 Description Disables interrupt request IRQ2 Enables interrupt request IRQ2 (initial value) Rev.3.00 Jul. 19, 2007 page 77 of 532 REJ09B0397-0300 3. Exception Handling Interrupt Enable Register 2 (IENR2) Bit 7 IENDT Initial value Read/Write Note: * 0 R/W 6 IENAD 0 R/W 5 0 R/W 4 0 R/W 3 IENTFH 0 R/W 2 IENTFL 0 R/W 1 IENTC* 0 R/W 0 IENTB 0 R/W Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to 0. IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7--Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer interrupt requests. Bit 7: IENDT 0 1 Description Disables direct transfer interrupt requests Enables direct transfer interrupt requests (initial value) Bit 6--A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter interrupt requests. Bit 6: IENAD 0 1 Description Disables A/D converter interrupt requests Enables A/D converter interrupt requests (initial value) Bits 5 and 4--Reserved Bits: Bits 5 and 4 are reserved; they should always be cleared to 0. Bit 3--Timer FH Interrupt Enable (IENTFH): Bit 3 enables or disables timer FH compare match and overflow interrupt requests. Bit 3: IENTFH 0 1 Description Disables timer FH interrupts Enables timer FH interrupts (initial value) Rev.3.00 Jul. 19, 2007 page 78 of 532 REJ09B0397-0300 3. Exception Handling Bit 2--Timer FL Interrupt Enable (IENTFL): Bit 2 enables or disables timer FL compare match and overflow interrupt requests. Bit 2: IENTFL 0 1 Description Disables timer FL interrupts Enables timer FL interrupts (initial value) Bit 1--Timer C Interrupt Enable (IENTC): Bit 1 is used in the H8/3857 Group to enable or disable timer C overflow or underflow interrupt requests. In the H8/3854 Group, this bit must always be cleared to 0. Bit 1: IENTC 0 1 Description Disables timer C interrupts Enables timer C interrupts (initial value) Bit 0--Timer B Interrupt Enable (IENTB): Bit 0 enables or disables timer B overflow or underflow interrupt requests. Bit 0: IENTB 0 1 Description Disables timer B interrupts Enables timer B interrupts (initial value) SCI3 interrupt control is covered in 10.4.2, in the description of serial control register 3 (SCR3). Interrupt request register 1 (IRR1) Bit 7 IRRTA Initial value Read/Write 0 R/W* 1 6 IRRS1* 0 R/W* 1 2 5 1 4 IRRI4 0 R/W* 1 3 IRRI3 0 R/W* 1 2 IRRI2* 0 R/W* 1 2 1 IRRI1 0 R/W* 1 0 IRRI0 0 R/W*1 Notes: 1. Only a write of 0 for flag clearing is possible. 2. Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to 0. IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A, SCI1, or IRQ4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Rev.3.00 Jul. 19, 2007 page 79 of 532 REJ09B0397-0300 3. Exception Handling Bit 7--Timer A Interrupt Request Flag (IRRTA) Bit 7: IRRTA 0 1 Description Clearing condition: When IRRTA = 1, it is cleared by writing 0 (initial value) Setting condition: When the timer A counter value overflows (goes from H'FF to H'00) Bit 6--SCI1 Interrupt Request Flag (IRRS1): Bit 6 is used in the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to 0. Bit 6: IRRS1 0 1 Description Clearing condition: When IRRS1 = 1, it is cleared by writing 0 Setting condition: When an SCI1 transfer is completed (initial value) Bit 5--Reserved Bit: Bit 5 is reserved; it is always read as 1, and cannot be modified. Bits 4, 3, 1, and 0--IRQ4, IRQ3, IRQ1, and IRQ0 Interrupt Request Flags (IRRI4, IRRI3, IRRI1, IRRI0) Bit n: IRRIn 0 1 Description Clearing condition: When IRRIn = 1, it is cleared by writing 0 to IRRIn (initial value) Setting condition: IRRIn is set when pin IRQn is set to interrupt input, and the designated signal edge is detected Note: n = 4, 3, 1, or 0 Bit 2--IRQ2 Interrupt Request Flag (IRRI2): Bit 2 is used in the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to 0. Bit 2: IRRI2 0 1 Description Clearing condition: When IRRI2 = 1, it is cleared by write 0 to IRRI2 (initial value) Setting condition: IRRI2 is set when pin IRQ2 is set to interrupt input, and the designated signal edge is detected Rev.3.00 Jul. 19, 2007 page 80 of 532 REJ09B0397-0300 3. Exception Handling Interrupt Request Register 2 (IRR2) Bit 7 IRRDT Initial value Read/Write 0 R/W* 1 6 IRRAD 0 R/W* 1 5 0 4 0 3 2 1 2 0 IRRTB 0 1 IRRTFH IRRTFL IRRTC* 0 R/W* 1 0 R/W* 1 0 R/W* R/W*1 Notes: 1. Only a write of 0 for flag clearing is possible. 2. Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to 0. IRR2 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a direct transfer, A/D converter, timer FH, timer FL, timer C, or timer B interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7--Direct Transfer Interrupt Request Flag (IRRDT) Bit 7: IRRDT 0 1 Description Clearing condition: When IRRDT = 1, it is cleared by writing 0 (initial value) Setting condition: When DTON = 1 and a direct transfer is made immediately after a SLEEP instruction is executed Bit 6--A/D Converter Interrupt Request Flag (IRRAD) Bit 6: IRRAD 0 1 Description Clearing condition: When IRRAD = 1, it is cleared by writing 0 Setting condition: When A/D conversion is completed and ADSF is reset (initial value) Bits 5 and 4--Reserved Bits: Bits 5 and 4 are reserved; they should always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 81 of 532 REJ09B0397-0300 3. Exception Handling Bit 3--Timer FH Interrupt Request Flag (IRRTFH) Bit 3: IRRTFH 0 1 Description Clearing condition: When IRRTFH = 1, it is cleared by writing 0 (initial value) Setting condition: When counter FH matches output compare register FH in 8-bit timer mode, or when 16-bit counter F (TCFL, TCFH) matches output compare register F (OCRFL, OCRFH) in 16-bit timer mode Bit 2--Timer FL Interrupt Request Flag (IRRTFL) Bit 2: IRRTFL 0 1 Description Clearing condition When IRRTFL = 1, it is cleared by writing 0 (initial value) Setting condition: When counter FL matches output compare register FL in 8-bit timer mode Bit 1--Timer C Interrupt Request Flag (IRRTC): Bit 1 is used in the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to 0. Bit 1: IRRTC 0 1 Description Clearing condition: When IRRTC = 1, it is cleared by writing 0 (initial value) Setting condition: When the timer C counter value overflows (goes from H'FF to H'00) or underflows (goes from H'00 to H'FF) Bit 0--Timer B Interrupt Request Flag (IRRTB) Bit 0: IRRTB 0 1 Description Clearing condition: When IRRTB = 1, it is cleared by writing 0 (initial value) Setting condition: When the timer B counter value overflows (goes from H'FF to H'00) Rev.3.00 Jul. 19, 2007 page 82 of 532 REJ09B0397-0300 3. Exception Handling Wakeup Interrupt Request Register (IWPR) Bit 7 IWPF7 Initial value Read/Write Note: * 0 R/W* 6 IWPF6 0 R/W* 5 IWPF5 0 R/W* 4 IWPF4 0 R/W* 3 IWPF3 0 R/W* 2 IWPF2 0 R/W* 1 IWPF1 0 R/W* 0 IWPF0 0 R/W* Only a write of 0 for flag clearing is possible. IWPR is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins WKP to WKP0 are set to wakeup input and a pin receives a falling edge input. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. 7 Bits 7 to 0--Wakeup Interrupt Request Flags (WKPF7 to WKPF0) Bit n: IWPFn 0 1 Description Clearing condition: When IWPFn = 1, it is cleared by writing 0 to IWPFn Setting condition: IWPFn is set when pin WKPn is set to wakeup interrupt input, and a falling edge input is detected at the pin Note: n = 7 to 0 3.3.3 External Interrupts The H8/3857 Group has 13 external interrupt sources, WKP7 to WKP0, and IRQ4 to IRQ0. The H8/3854 Group has 12 external interrupt sources, WKP7 to WKP0, IRQ4, IRQ3, IRQ1, and IRQ0. Interrupts WKP0 to WKP7: Interrupts WKP0 to WKP7 are requested by falling edge inputs at pins WKP0 to WKP7. When these pins are designated as WKP0 to WKP7 pins in port mode register 5 (PMR5) and falling edge input is detected, the corresponding bit in the wakeup interrupt request register (IWPR) is set to 1, requesting an interrupt. Wakeup interrupt requests can be disabled by clearing the IENWP bit in IENR1 to 0. It is also possible to mask all interrupts by setting the CCR I bit to 1. When an interrupt exception handling request is received for interrupts WKP0 to WKP7, the CCR I bit is set to 1. The vector number for interrupts WKP0 to WKP7 is 9. Since all eight interrupts are assigned the same vector number, the interrupt source must be determined by the exception handling routine. Rev.3.00 Jul. 19, 2007 page 83 of 532 REJ09B0397-0300 3. Exception Handling Interrupts IRQ0 to IRQ4: Interrupts IRQ0 to IRQ4 are requested by into pins inputs to IRQ0 to IRQ4. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR). The IRQ2 interrupt is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. When these pins are designated as pins IRQ0 to IRQ4 in port mode registers 1 and 2 (PMR1 and PMR2) and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Interrupts IRQ0 to IRQ4 can be disabled by clearing bits IEN0 to IEN4 in IENR1 to 0. All interrupts can be masked by setting the I bit in CCR to 1. When IRQ0 to IRQ4 interrupt exception handling is initiated, the I bit is set to 1. Vector numbers 4 to 8 are assigned to interrupts IRQ0 to IRQ4. The order of priority is from IRQ0 (high) to IRQ4 (low). Table 3.2 gives details. In the H8/3854 Group, exception handling vector number 6 is reserved. 3.3.4 Internal Interrupts There are 16 internal interrupts that can be requested by the on-chip peripheral modules in the H8/3857 Group, and 14 in the H8/3854 Group. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0. All interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt request is accepted, the I bit is set to 1. Vector numbers 10 to 20 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip peripheral modules. In the H8/3854 Group, exception handling vector numbers 10 and 13 are reserved. 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. Interrupt operation is described as follows. * When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. * When the interrupt controller receives an interrupt request, it sets the interrupt request flag. * From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2 for a list of interrupt priorities.) * The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending. Rev.3.00 Jul. 19, 2007 page 84 of 532 REJ09B0397-0300 3. Exception Handling * If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. * The I bit of CCR is set to 1, masking all further interrupts. * The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (I = 1). 2. If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. Interrupt controller External or internal interrupts Priority decision logic Interrupt request External interrupts or internal interrupt enable signals I CCR (CPU) Figure 3.2 Block Diagram of Interrupt Controller Rev.3.00 Jul. 19, 2007 page 85 of 532 REJ09B0397-0300 3. Exception Handling Program execution state IRRI0 = 1 Yes IEN0 = 1 Yes No No No IRRI1 = 1 Yes IEN1 = 1 Yes No No IRRI2 = 1* Yes IEN2 = 1* Yes No IRRDT = 1 Yes IENDT = 1 Yes No No No I=0 Yes PC contents saved CCR contents saved I1 Branch to interrupt handling routine Legend: PC: CCR: I: Program counter Condition code register I bit of CCR Note: * The IRQ2, SCI1, and timer C interrupts are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group. Figure 3.3 Flow up to Interrupt Acceptance Rev.3.00 Jul. 19, 2007 page 86 of 532 REJ09B0397-0300 3. Exception Handling SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area SP (R7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR* PCH PCL Even address Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling Legend: PCH: Upper 8 bits of program counter (PC) PCL: Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. Register contents must always be saved and restored by word access, starting from an even-numbered address. * Ignored on return from interrupt. Figure 3.4 Stack State after Completion of Interrupt Exception Handling Figure 3.5 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. Rev.3.00 Jul. 19, 2007 page 87 of 532 REJ09B0397-0300 Interrupt is accepted 3. Exception Handling Interrupt level decision and wait for end of instruction Instruction prefetch Internal processing Stack access Vector fetch Prefetch instruction of Internal interrupt-handling routine processing Interrupt request signal Rev.3.00 Jul. 19, 2007 page 88 of 532 REJ09B0397-0300 (1) (3) (5) (6) (8) (9) (2) (4) (1) (7) (9) (10) Internal address bus Internal read signal Internal write signal Figure 3.5 Interrupt Sequence Internal data bus (16 bits) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector address) (10) First instruction of interrupt-handling routine 3. Exception Handling 3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Total Note: * Not including EEPMOV instruction. Interrupt Wait States States 1 to 13 4 2 4 4 15 to 27 3.4 3.4.1 Application Notes Notes on Stack Area Use When word data is accessed in the H8/3857 Group, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6. Rev.3.00 Jul. 19, 2007 page 89 of 532 REJ09B0397-0300 3. Exception Handling SP SP PCH PC L SP R1L PC L H'FEFC H'FEFD H'FEFF BSR instruction SP set to H'FEFF MOV. B R1L, @-R7 Contents of PCH are lost Stack accessed beyond SP Legend: PCH: Upper byte of program counter PCL: Lower byte of program counter R1L: General register R1L SP: Stack pointer Figure 3.6 Operation when Odd Address Is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored. 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls these pins (IRQ4, IRQ3, IRQ2*, IRQ1, IRQ0, and WKP7 to WKP0), the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching pin functions. Table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way. Note: * Applies to the H8/3857 Group; not provided in the H8/3854 Group. Rev.3.00 Jul. 19, 2007 page 90 of 532 REJ09B0397-0300 3. Exception Handling Table 3.5 Conditions under which Interrupt Request Flag Is Set to 1 Conditions * * IRRI3 * * IRRI2* * * IRRI1 * * IRRI0 * * When PMR2 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR bit IEG4 = 0. When PMR2 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR bit IEG4 = 1. When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit IEG3 = 0. When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit IEG3 = 1. When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR bit IEG2 = 0. When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR bit IEG2 = 1. When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit IEG1 = 0. When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit IEG1 = 1. When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR bit IEG0 = 0. When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR bit IEG0 = 1. Interrupt Request Flags Set to 1 IRR1 IRRI4 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low Note: * Applies to the H8/3857 Group. In the H8/3854 Group, this flag must always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 91 of 532 REJ09B0397-0300 3. Exception Handling Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) CCR I bit 1 Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 CCR I bit 0 Interrupt mask cleared Figure 3.7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure Rev.3.00 Jul. 19, 2007 page 92 of 532 REJ09B0397-0300 4. Clock Pulse Generators Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 Block Diagram Figure 4.1 shows a block diagram of the clock pulse generators. OSC /2 System clock divider (1/2) System clock OSC /16 divider (1/8) /2 to /8192 W SUB W/2 W/4 W/8 Subclock pulse generator Prescaler W (5 bits) to W/128 OSC 1 OSC 2 System clock oscillator OSC (fOSC ) System clock pulse generator Prescaler S (13 bits) X1 X2 Subclock oscillator W (f W ) W /2 Subclock divider (1/2, 1/4, 1/8) W /4 W /8 Figure 4.1 Block Diagram of Clock Pulse Generators 4.1.2 System Clock and Subclock The basic clock signals that drive the CPU and on-chip peripheral modules are and SUB. Four of the clock signals have names: is the system clock, SUB is the subclock, OSC is the oscillator clock, and W is the watch clock. Rev.3.00 Jul. 19, 2007 page 93 of 532 REJ09B0397-0300 4. Clock Pulse Generators The clock signals available for use by peripheral modules are /2, /4, /8, /16, /32, /64, /128, /256, /512, /1024, /2048, /4096, /8192, W, W/2, W/4, W/8, W/16, W/32, W/64, and W/128. The clock requirements differ from one module to another. 4.2 System Clock Generator Clock pulse can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. Connecting a Crystal Oscillator: Figure 4.2 shows a typical method of connecting a crystal oscillator. C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% C1 = C 2 = 12 pF 20% Figure 4.2 Typical Connection to Crystal Oscillator Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the characteristics given in table 4.1 should be used. CS LS OSC 1 RS OSC 2 C0 Figure 4.3 Equivalent Circuit of Crystal Oscillator Table 4.1 Crystal Oscillator Parameters 2 500 7 pF 4 100 7 pF 8 50 7 pF 10 30 7 pF Frequency (MHz) Rs (max) C0 (max) Rev.3.00 Jul. 19, 2007 page 94 of 532 REJ09B0397-0300 4. Clock Pulse Generators Connecting a Ceramic Oscillator: Figure 4.4 shows a typical method of connecting a ceramic oscillator. C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% C1 = 30 pF 10% C2 = 30 pF 10% Ceramic oscillator: Murata Figure 4.4 Typical Connection to Ceramic Oscillator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4.5.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2. To be avoided Signal A Signal B C1 OSC 1 OSC 2 C2 Figure 4.5 Board Design of Oscillator Circuit Rev.3.00 Jul. 19, 2007 page 95 of 532 REJ09B0397-0300 4. Clock Pulse Generators Inputting an External Clock: When inputting an external clock, connect it to the OSC1 pin via a resistance R, and leave the OSC2 pin open. An example of the connection in this case is shown in figure 4.6. R OSC1 External clock input OSC2 Open R = 500 30% Figure 4.6 Example of Connection when Inputting an External Clock Frequency Duty OSC clock (osc) 45% to 55% 4.3 Subclock Generator Connecting a 32.768-kHz Crystal Oscillator: Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4.7. Following the same connection precautions as mentioned in Notes on Board Design in section 4.2, System Clock Generator. C1 X1 X2 C2 C1 = C 2 = 15 pF (typ.) Figure 4.7 Typical Connection to 32.768-kHz Crystal Oscillator Rev.3.00 Jul. 19, 2007 page 96 of 532 REJ09B0397-0300 4. Clock Pulse Generators Figure 4.8 shows the equivalent circuit of the 32.768-kHz crystal oscillator. CS LS X1 RS X2 C0 C0 = 1.5 pF typ RS = 14 k typ f W = 32.768 kHz Crystal oscillator: MX38T (Nihon Denpa Kogyo) Figure 4.8 Equivalent Circuit of 32.768-kHz Crystal Oscillator Inputting an External Clock * Circuit configuration An external clock is input to the X1 pin. The X2 pin should be left open. An example of the connection in this case is shown in figure 4.9. External clock input X1 X2 Open Figure 4.9 Example of Connection when Inputting an External Clock * External clock Input a square waveform to the X1 pin. When using the CPU, timer A, timer C*, or an LCD, with a subclock (w) clock selected, do not stop the clock supply to the X1 pin. Note: * This is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. Rev.3.00 Jul. 19, 2007 page 97 of 532 REJ09B0397-0300 4. Clock Pulse Generators txH VIH VIL txL txr txf Figure 4.10 External Subclock Timing The DC characteristics and timing of an external clock input to the X1 pin are shown in table 4.2. Table 4.2 DC Characteristics and Timing (VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F and H8/3857 Group, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to + 75C*, unless otherwise specified, including subactive mode) Applicable Symbol Pin VIH VIL txr txf fx = 32.768 kHz X1 Test Conditions Values Min VCC -0.3 -0.3 12.0 12.0 fx = 38.4 kHz 10.0 10.0 Typ 32.768 38.4 Max VCC +0.3 0.3 100 100 kHz s Figure 4.10 kHz s Figure 4.10 ns Figure 4.10 Unit Notes V Figure 4.10 Item Input high voltage Input low voltage External subclock rise time External subclock fall time External subclock fx oscillation frequency External subclock high width External subclock low width txH txL External subclock fx oscillation frequency External subclock high width External subclock low width txH txL Note: * The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 98 of 532 REJ09B0397-0300 4. Clock Pulse Generators 4.4 Prescalers The H8/3857 Group and H8/3854 Group are equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock () as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 32.768-kHz signal divided by 4 (W/4) as its input clock. Its prescaled outputs are used by timer A as a time base for timekeeping. Prescaler S (PSS): Prescaler S is a 13-bit counter using the system clock () as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by timer A, timer B, timer C*, timer F, SCI1*, SCI3, the A/D converter, LCD controller, and 14-bit PWM*. The divider ratio can be set separately for each on-chip peripheral function. In active (medium-speed) mode the clock input to prescaler S is OSC/16. Note: * This is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. Prescaler W (PSW): Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (W/4) as its input clock. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base for timekeeping. Rev.3.00 Jul. 19, 2007 page 99 of 532 REJ09B0397-0300 4. Clock Pulse Generators 4.5 Note on Oscillators Oscillator characteristics of both the mask ROM and F-ZTAT versions are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. Rev.3.00 Jul. 19, 2007 page 100 of 532 REJ09B0397-0300 5. Power-Down Modes Section 5 Power-Down Modes 5.1 Overview The H8/3857 Group and H8/3854 Group have seven modes of operation after a reset. These include six power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the seven operation modes. Table 5.1 Operation Modes Description The CPU runs on the system clock, executing program instructions at high speed The CPU runs on the system clock, executing program instructions at reduced speed The CPU runs on the subclock, executing program instructions at reduced speed The CPU halts. On-chip peripheral modules continue to operate on the system clock. The CPU halts. Timer A, timer C*, and the LCD controller continue to operate on the subclock. The CPU halts. The time-base function of timer A and the LCD controller continue to operate on the subclock. The CPU and all on-chip peripheral modules stop operating Operating Mode Active (high-speed) mode Active (medium-speed) mode Subactive mode Sleep mode Subsleep mode Watch mode Standby mode Note: * This is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. All the above operating modes except active (high-speed) mode are referred to as power-down modes. In this section the two active modes (high-speed and medium-speed) are referred to collectively as active mode. Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal states in each mode. Rev.3.00 Jul. 19, 2007 page 101 of 532 REJ09B0397-0300 5. Power-Down Modes Program execution state Reset state LSON = 0, MSON = 0 Program halt state st ru Program halt state Active (high-speed) mode *1 n P i on EE uct SL str in SL in SL io n EE P st ru ct LSON = 0, MSON = 1 Active (medium-speed) mode *4 *1 SSBY = 1, TMA3 = 1 N TO D = 1 Watch mode S E LE P in u str cti on = 1 N TO D *1 in st ru P N TO D *3 ct io EE EE P = n Standby mode SL in st ru ct io n SSBY = 1, TMA3 = 0, LSON = 0 P in ct io EE *4 *3 SSBY = 0, LSON = 0 SL 1 Sleep mode SL EE P in LSON = 1, TMA3 = 1 st ru ct SLEEP instruction *2 SSBY = 0, LSON = 1, TMA3 = 1 io n Subactive mode Subsleep mode : Transition caused by exception handling Power-down mode 1. A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that the interrupt is accepted and interrupt handling is performed. 2. Details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 through 5.8. 3. The module standby mode for the LCD controller is initiated by setting a register within the LCD controller itself, and so is not shown in this diagram. Notes: 1. 2. 3. 4. * Timer A interrupt, IRQ0 interrupt, WKP0 to WKP7 interrupts Timer A interrupt, timer C interrupt*, timer IRQ0 to IRQ4 interrupts*, WKP0 to WKP7 interrupts All interrupts* IRQ0 interrupt, IRQ1 interrupt, WKP0 to WKP7 interrupts The timer C, SCI1, and IRQ2 interrupts are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group. Figure 5.1 Operation Mode Transition Diagram Rev.3.00 Jul. 19, 2007 page 102 of 532 REJ09B0397-0300 5. Power-Down Modes Table 5.2 Internal State in Each Operation Mode Active Mode Function High Speed Medium Speed Functions Functions Functions Sleep Mode Functions Functions Halted Retained Watch Mode Halted Functions Halted Retained Subactive Subsleep Mode Mode Halted Functions Functions Halted Functions Halted Retained Standby Mode Halted Functions Halted Retained Retained* 1 System clock oscillator Functions Subclock oscillator CPU operation RAM Registers I/O External interrupts IRQ0 IRQ1 IRQ2* IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Peripheral Timer A module Timer B functions 6 Timer C* Timer F SCI1* SCI3 PWM* A/D LCD* Notes: 1. 2. 3. 4. 5. 5 6 6 6 Functions Instructions Functions Functions Functions Functions Functions Retained* 4 Functions Functions Functions Retained* 4 Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions* Functions* Functions* Retained Retained Retained Retained Functions/ Functions/ 2 2 Retained* Retained* Retained Retained Retained Reset Retained Retained Functions Retained Reset Retained Retained Retained 3 3 3 Functions Functions Functions Functions Functions Functions Functions Functions Functions Retained Functions Functions Retained Reset Retained Retained Functions Retained Reset Retained Retained Functions Register contents held; high-impedance output. Functions only if external clock or W/4 internal clock is selected; otherwise halted and retained. Functions when timekeeping time-base function is selected. External interrupt requests are ignored. The interrupt request register contents are not affected. In module standby mode, only the clock supplied to the LCD controller is stopped. Register values are retained, and all outputs go to the VSS potential. 6. This is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. Rev.3.00 Jul. 19, 2007 page 103 of 532 REJ09B0397-0300 5. Power-Down Modes 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 Name System control register 1 System control register 2 System Control Register Abbreviation SYSCR1 SYSCR2 R/W R/W R/W Initial Value H'07 H'E0 Address H'FFF0 H'FFF1 System Control Register 1 (SYSCR1) Bit 7 SSBY Initial value Read/Write 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W 2 1 1 1 0 1 SYSCR1 is an 8-bit read/write register for control of the power-down modes. Bit 7--Software Standby (SSBY): This bit designates transition to standby mode or watch mode. Bit 7: SSBY 0 Description * * 1 * * When a SLEEP instruction is executed in active mode, a transition is made to sleep mode (initial value) When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode. When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode. When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode. Rev.3.00 Jul. 19, 2007 page 104 of 532 REJ09B0397-0300 5. Power-Down Modes Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 10 ms. Bit 6: STS2 0 Bit 5: STS1 0 Bit 4: STS0 0 1 1 0 1 1 * * Legend: * Don't care Description Wait time = 8,192 states Wait time = 16,384 states Wait time = 32,768 states Wait time = 65,536 states Wait time = 131,072 states (initial value) Bit 3--Low Speed on Flag (LSON): This bit chooses the system clock () or subclock (SUB) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3: LSON 0 1 Description The CPU operates on the system clock () The CPU operates on the subclock (SUB) (initial value) Bits 2 to 0--Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified. System Control Register 2 (SYSCR2) Bit 7 Initial value Read/Write 1 6 1 5 1 4 NESEL 0 R/W 3 DTON 0 R/W 2 MSON 0 R/W 1 SA1 0 R/W 0 SA0 0 R/W SYSCR2 is an 8-bit read/write register for power-down mode control. Bits 7 to 5--Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified. Rev.3.00 Jul. 19, 2007 page 105 of 532 REJ09B0397-0300 5. Power-Down Modes Bit 4--Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency at which the watch clock signal (W) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (OSC) generated by the system clock pulse generator. When OSC = 2 to 10 MHz, clear NESEL to 0. Bit 4: NESEL 0 1 Description Sampling rate is OSC/16 Sampling rate is OSC/4 (initial value) Bit 3--Direct Transfer on Flag (DTON): This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits. Bit 3: DTON 0 Description When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. (initial value) When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. 1 When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1. Bit 2--Medium Speed on Flag (MSON): After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. Bit 2: MSON 0 1 Description Operation is in active (high-speed) mode Operation is in active (medium-speed) mode (initial value) Rev.3.00 Jul. 19, 2007 page 106 of 532 REJ09B0397-0300 5. Power-Down Modes Bits 1 and 0--Subactive Mode Clock Select (SA1, SA0): These bits select the CPU clock rate (W/2, W/4, or W/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1: SA1 0 Bit 0: SA0 0 1 1 * Legend: * Don't care Description W/8 W/4 W/2 (initial value) 5.2 5.2.1 Sleep Mode Transition to Sleep Mode The system goes from active mode to sleep mode when a SLEEP instruction is executed while the SSBY and LSON bits in system control register 1 (SYSCR1) are cleared to 0. In sleep mode CPU operation is halted but the on-chip peripheral functions other than PWM* are operational. The CPU register contents are retained. Note: * This is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. 5.2.2 Clearing Sleep Mode Sleep mode is cleared by an interrupt (timer A, timer B, timer C*, timer F, IRQ0, IRQ1, IRQ2*, IRQ3, IRQ4, WKP0 to WKP7, SCI1*, SCI3, A/D converter) or by input at the RES pin. Note: * The timer C, SCI1, and IRQ2 interrupts are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group. Clearing by Interrupt: When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register. Clearing by RES Input: When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Rev.3.00 Jul. 19, 2007 page 107 of 532 REJ09B0397-0300 5. Power-Down Modes 5.3 5.3.1 Standby Mode Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. As long as a minimum required voltage is applied, the contents of CPU registers and some on-chip peripheral registers, and data in the on-chip RAM, are retained. Data in the on-chip RAM will be retained as long as the specified RAM data retention voltage is supplied. The I/O ports go to the high-impedance state. 5.3.2 Clearing Standby Mode Standby mode is cleared by an interrupt (IRQ0, IRQ1, WKP0 to WKP7) or by input at the RES pin. Clearing by Interrupt: When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2-STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (mediumspeed) mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. Clearing by RES Input: When the RES pin goes low, the system clock pulse generator starts. After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin should be kept at the low level until the pulse generator output stabilizes. 5.3.3 Oscillator Settling Time after Standby Mode Is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. * When a Crystal Oscillator is Used The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a waiting time of at least 10 ms. Rev.3.00 Jul. 19, 2007 page 108 of 532 REJ09B0397-0300 5. Power-Down Modes Table 5.4 STS2 0 Clock Frequency and Settling Time (Times are in ms) STS1 0 STS0 0 1 1 0 1 * Waiting Time 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 5 MHz 1.6 3.2 6.6 13.1 26.2 4 MHz 2.0 4.1 8.2 16.4 32.8 2 MHz 4.1 8.2 16.4 32.8 65.5 1 MHz 8.2 16.4 32.8 65.5 131.1 0.5 MHz 16.4 32.8 65.5 131.1 262.1 1 * Legend: * Don't care * When an External Clock is Used Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set. 5.3.4 Transition to Standby Mode and Port Pin States The system goes from active (high-speed or medium-speed) mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in TMA is cleared to 0. Port pins (except those with their MOS pull-up turned on) enter high-impedance state when the transition to standby mode is made. This timing is shown in figure 5.2. Internal data bus SLEEP instruction fetch Next instruction fetch SLEEP instruction execution Internal processing Port pins Output Active (high-speed or medium-speed) mode High-impedance Standby mode Figure 5.2 Transition to Standby Mode and Port Pin States Rev.3.00 Jul. 19, 2007 page 109 of 532 REJ09B0397-0300 5. Power-Down Modes 5.3.5 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ or WKP is input, both the high- and low-level widths of the signal must be at least two cycles of system clock or subclock SUB (referred to together in this section as the internal clock). As the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. Ensure that external input signals conform to the conditions stated in 3, Recommended timing of external input signals, below 2. When external input signals cannot be captured because internal clock stops The case of falling edge capture is illustrated in figure 5.3 As shown in the case marked "Capture not possible," when an external input signal falls immediately after a transition to active (high-speed or medium-speed) mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc. 3. Recommended timing of external input signals To ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in "Capture possible: case 1." External input signal capture is also possible with the timing shown in "Capture possible: case 2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured. Rev.3.00 Jul. 19, 2007 page 110 of 532 REJ09B0397-0300 5. Power-Down Modes Operating mode Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc tcyc tsubcyc Wait for Active (high-speed, Standby mode oscillation medium-speed) mode or watch mode to settle or subactive mode tcyc tsubcyc tcyc tsubcyc or SUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signall Figure 5.3 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode 4. Input pins to which these notes apply: IRQ4, IRQ3, IRQ2*, IRQ1, IRQ0, WKP7 to WKP0, ADTRG, TMIB, TMIC*, TMIF Note: * H8/3857 Group pin, not provided in the H8/3854 Group. 5.4 5.4.1 Watch Mode Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules other than timer A and the LCD controller is halted. The LCD controller can be selected to operate or to halt. As long as a minimum required voltage is applied, the contents of CPU registers and some registers of the onchip peripheral modules, and the on-chip RAM contents, are retained. I/O ports keep the same states as before the transition. Rev.3.00 Jul. 19, 2007 page 111 of 532 REJ09B0397-0300 5. Power-Down Modes 5.4.2 Clearing Watch Mode Watch mode is cleared by an interrupt (timer A, IRQ0, WKP0 to WKP7) or by a input at the RES pin. Clearing by Interrupt: Watch mode is cleared when an interrupt is requested. The mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2-STS0 has elapsed, a stable clock signal is supplied to the entire chip, and interrupt exception handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. Clearing by RES Input: Clearing by RES pin is the same as for standby mode; see section 5.3.2, Clearing Standby Mode. 5.4.3 Oscillator Settling Time after Watch Mode Is Cleared The waiting time is the same as for standby mode; see section 5.3.3, Oscillator Settling Time after Standby Mode is Cleared. 5.4.4 Notes on External Input Signal Changes before/after Watch Mode See section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 5.5 5.5.1 Subsleep Mode Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than timer A, timer C*, and the LCD controller is halted. As long as a minimum required voltage is applied, the contents of CPU registers and some registers of the on-chip peripheral modules, and the on-chip RAM contents, are retained. I/O ports keep the same states as before the transition. Note: * This is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. Rev.3.00 Jul. 19, 2007 page 112 of 532 REJ09B0397-0300 5. Power-Down Modes 5.5.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (timer A, timer C*, IRQ0, IRQ1, IRQ2*, IRQ3, IRQ4, WKP0 to WKP7) or by a low input at the RES pin. Note: * The timer C and IRQ2 interrupts are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group. Clearing by Interrupt: When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. Clearing by RES Input: Clearing by RES pin is the same as for standby mode; see section 5.3.2, Clearing Standby Mode. 5.6 5.6.1 Subactive Mode Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, IRQ0, or WKP0 to WKP7 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C*, IRQ0, IRQ1, IRQ2*, IRQ3, IRQ4, or WKP0 to WKP7 interrupt is requested. A transition to subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. Note: * The timer C and IRQ2 interrupts are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group. 5.6.2 Clearing Subactive Mode Subactive mode is cleared by a SLEEP instruction or by a input at the RES pin. Clearing by SLEEP Instruction: If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct Transfer, below. Clearing by RES Pin: Clearing by RES pin is the same as for standby mode; see Clearing by RES pin in section 5.3.2, Clearing Standby Mode. Rev.3.00 Jul. 19, 2007 page 113 of 532 REJ09B0397-0300 5. Power-Down Modes 5.6.3 Operating Frequency in Subactive Mode The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are W/2, W/4, and W/8. 5.7 5.7.1 Active (medium-speed) Mode Transition to Active (medium-speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0, IRQ1, or WKP0 to WKP7 interrupts in standby mode, timer A, IRQ0, or WKP0 to WKP7 interrupts in watch mode, or any interrupt in sleep mode. A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.7.2 Clearing Active (medium-speed) Mode Active (medium-speed) mode is cleared by a SLEEP instruction or by a input at the RES pin. Clearing by SLEEP Instruction: A transition to standby mode takes place if a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and TMA3 bit in TMA is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1 when a SLEEP instruction is executed. Sleep mode is entered if both SSBY and LSON are cleared to 0 when a SLEEP instruction is executed. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See section 5.8, Direct Transfer, below for details. Clearing by RES Pin: When the RES pin goes low, the CPU enters the reset state and active (medium-speed) mode is cleared. 5.7.3 Operating Frequency in Active (medium-speed) Mode In active (medium-speed) mode, the CPU is clocked at 1/8 the frequency in active (high-speed) mode. Rev.3.00 Jul. 19, 2007 page 114 of 532 REJ09B0397-0300 5. Power-Down Modes 5.8 5.8.1 Direct Transfer Direct Transfer Overview The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt exception handling starts. If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. Direct Transfer from Active (High-Speed) Mode to Active (Medium-Speed) Mode: When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. Direct Transfer from Active (Medium-Speed) Mode to Active (High-Speed) Mode: When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. Direct Transfer from Active (High-Speed) Mode to Subactive Mode: When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. Direct Transfer from Subactive Mode to Active (High-Speed) Mode: When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. Direct Transfer from Active (Medium-Speed) Mode to Subactive Mode: When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. Rev.3.00 Jul. 19, 2007 page 115 of 532 REJ09B0397-0300 5. Power-Down Modes Direct Transfer from Subactive Mode to Active (Medium-Speed) Mode: When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. 5.8.2 Calculation of Direct Transfer Time before Transition Time Required before Direct Transfer from Active (High-speed) Mode to Active (MediumSpeed) Mode: A direct transfer is made from active (high-speed) mode to active (medium-speed) mode when a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to interrupt exception handling completion is calculated by expression (1) below. Direct transfer time = (number of states for SLEEP instruction execution + number of states for internal processing) x tcyc before transition + number of states for interrupt exception handling execution x tcyc after transition ...... (1) Example: Direct transfer time for the H8/3857 Group and H8/3854 Group = (2 + 1) x 2tosc + 14 x 16tosc = 230 tosc Legend: tosc: OSC clock cycle time tcyc: System clock () cycle time Time Required before Direct Transfer from Active (Medium-Speed) Mode to Active (HighSpeed) Mode: A direct transfer is made from active (medium-speed) mode to active (high-speed) mode when a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to interrupt exception handling completion is calculated by expression (2) below. Direct transfer time = (number of states for SLEEP instruction execution + number of states for internal processing) x tcyc before transition + number of states for interrupt exception handling execution x tcyc after transition ...... (2) Rev.3.00 Jul. 19, 2007 page 116 of 532 REJ09B0397-0300 5. Power-Down Modes Example: Direct transfer time for the H8/3857 Group and H8/3854 Group = (2 + 1) x 16tosc + 14 x 2tosc = 76 tosc Legend: tosc: OSC clock cycle time tcyc: System clock () cycle time Time Required before Direct Transfer from Subactive Mode to Active (High-Speed) Mode: A direct transfer is made from subactive mode to active (high-speed) mode when a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to interrupt exception handling completion is calculated by expression (3) below. Direct transfer time = (number of states for SLEEP instruction execution + number of states for internal processing) x tsubcyc before transition + (wait time designated by STS2 to STS0 bits in SCR + number of states for interrupt exception handling execution) x tcyc after transition ...... (3) Example: Direct transfer time for the H8/3857 Group and H8/3854 Group (when CPU clock frequency is w/8 and wait time is 8192 states) = (2 + 1) x 8tw + (8192 + 14) x 2tosc = 24tw + 16412tosc Legend: tosc: tw: tcyc: tsubcyc: OSC clock cycle time Watch clock cycle time System clock () cycle time Subclock (SUB) cycle time Time Required before Direct Transfer from Subactive Mode to Active (Medium-Speed) Mode: A direct transfer is made from subactive mode to active (medium-speed) mode when a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON and DTON bits in SYSCR2 are set to 1, and the TMA3 bit in TMA is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to interrupt exception handling completion is calculated by expression (4) below. Direct transfer time = (number of states for SLEEP instruction execution + number of states for internal processing) x tsubcyc before transition + (wait time designated by STS2 to STS0 bits in SCR + number of states for interrupt exception handling execution) x tcyc after transition ...... (4) Rev.3.00 Jul. 19, 2007 page 117 of 532 REJ09B0397-0300 5. Power-Down Modes Example: Direct transfer time for the H8/3857 Group and H8/3854 Group (when CPU clock frequency is w/8 and wait time is 8192 states) = (2 + 1) x 8tw + (8192 + 14) x 16tosc = 24tw + 131296tosc Legend: tosc: tw: tcyc: tsubcyc: OSC clock cycle time Watch clock cycle time System clock () cycle time Subclock (SUB) cycle time 5.8.3 Notes on External Input Signal Changes before/after Direct Transition 1. Direct transition from active (high-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 2. Direct transition from active (medium-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 3. Direct transition from subactive mode to active (high-speed) mode Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 4. Direct transition from subactive mode to active (medium-speed) mode Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. Rev.3.00 Jul. 19, 2007 page 118 of 532 REJ09B0397-0300 6. ROM Section 6 ROM 6.1 Overview The H8/3857 has 60 kbytes of on-chip flash memory or mask ROM, while the H8/3856 has 48 kbytes, and the H8/3855 40 kbytes, of on-chip mask ROM. The H8/3854 has 60 kbytes of on-chip flash memory or 32 kbytes of on-chip mask ROM, while the H8/3853 has 24 kbytes, and the H8/3852 16 kbytes, of on-chip mask ROM. Note that the H8/3854 flash memory and mask ROM versions have different ROM sizes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state data access for both byte data and word data. With the flash memory versions (H8/3857F, H8/3854F), programs can be written and erased and programmed either with a general-purpose PROM programmer or on-board. When carrying out program development using the H8/3854F with the intention of mask ROM implementation, care must be taken with ROM and RAM sizes since the maximum sizes for the mask ROM version are 32 kbytes of ROM and 1 kbyte of RAM. 6.1.1 Block Diagram Figure 6.1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0002 H'0000 H'0002 H'0001 H'0003 On-chip ROM H'EDFE H'EDFE Even-numbered address H'EDFF Odd-numbered address Figure 6.1 ROM Block Diagram (60 kbytes) Rev.3.00 Jul. 19, 2007 page 119 of 532 REJ09B0397-0300 6. ROM 6.2 6.2.1 Overview of Flash Memory Features Features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. In block erasing, 1-kbyte, 28-kbyte, 16-kbyte, and 12-kbyte blocks can be set arbitrarily. * Programming/erase times The flash memory programming time is 10 ms (typ.)*1 for simultaneous 32-byte programming, equivalent to 300 s (typ.)*1 per byte, and the erase time is 100 ms (typ.)*2 per block. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment For data transfer in boot mode, the chip's bit rate can be automatically adjusted to match the transfer bit rate of the host (9600, 4800, or 2400 bps). * Protect modes There are three protect modeshardware, software, and errorwhich allow protected status to be designated for flash memory program/erase/verify operations. * Writer mode Flash memory can be programmed/erased in Writer mode, using a PROM programmer, as well as in on-board programming mode. Notes: 1. Shows the total time during which the P bit in flash memory control register 1 (FLMCR1) is set. The program-verify time is not included. 2. Shows the total time during which the E bit in flash memory control register 1 (FLMCR1) is set. The erase-verify time is not included. Rev.3.00 Jul. 19, 2007 page 120 of 532 REJ09B0397-0300 6. ROM 6.2.2 Block Diagram Internal data bus (lower 8 bits) Internal data bus (upper 8 bits) SYSCR3 FLMCR1 FLMCR2 EBR MDCR TEST2 pin TEST pin H'0000 H'0002 H'0004 H'0001 H'0003 H'0005 Bus interface/controller Operating mode FWE pin On-chip flash memory (60 kbytes) H'EDFC H'EDFE Upper byte (even address) Legend: SYSCR3 FLMCR1 FLMCR2 EBR H'EDFD H'EDFF Lower byte (odd address) : System control register 3* : Flash memory control register 1* : Flash memory control register 2* : Erase block register* Note: * The registers that control the flash memory (FLMCR1, FLMCR2, EBR, and MDCR) are for use exclusively by the flash memory version, and are not provided in the mask ROM version. In the mask ROM version, a read access to the address of a register other than MDCR will always return 0, a read access to the address (H'FF89) corresponding to MDCR will return an undefined value, and writes are invalid. Figure 6.2 Block Diagram of Flash Memory Rev.3.00 Jul. 19, 2007 page 121 of 532 REJ09B0397-0300 6. ROM 6.2.3 Flash Memory Operating Modes Mode Transition Diagram: When the TEST2, TEST, and FWE pins are set in the reset state and a reset start is effected, the chip enters one of the operating modes shown in figure 6.3. In user mode, the flash memory can be read but cannot be programmed or erased. Modes in which the flash memory can be programmed and erased are boot mode, user program mode, and Writer mode. 2= EST 0, T 0 = T= TES FWE =0 RES 1, Reset state FWE = 1, TEST2 = TEST = 0 User mode RES = 0 * TEST2 = 1, FWE = 1, SWE = 1 RES = 0 FWE = 0 or SWE = 0 User program mode RE S = 0 Writer mode Boot mode On-board programming mode Notes: Transitions between user mode and user program mode should only be made when the CPU is not accessing the flash memory. * TEST2 = 0, TEST = 1 PB6 = PB5 = 1 PB4 = 0 Figure 6.3 Flash Memory Related State Transitions Rev.3.00 Jul. 19, 2007 page 122 of 532 REJ09B0397-0300 6. ROM On-Board Programming Modes * Boot Mode 1. Initial state The flash memory is in the erased state when shipped. The procedure for rewriting an old version of an application program or data is described here. The user should prepare a programming control program and the new application program beforehand in the host. Host Programming control program New application program H8/3857F or H8/3854F Boot program Flash memory (RAM) SCI 2. Programming control program transfer When boot mode is entered, the boot program in the chip (already incorporated in the chip) is started, an SCI communication check is carried out, and the boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Programming control program New application program H8/3857F or H8/3854F Boot program Flash memory (RAM) Boot program area Application program (old version) Application program (old version) SCI 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host Programming control program New application program H8/3857F or H8/3854F Boot program Flash memory (RAM) Boot program area Flash memory erase SCI 4. Writing new application program The programming control program in the host is transferred to RAM by SCI communication and executed, and the new application program in the host is written into the flash memory. Host H8/3857F or H8/3854F Boot program Flash memory (RAM) Programming control program New application program SCI Program execution state Figure 6.4 Boot Mode Rev.3.00 Jul. 19, 2007 page 123 of 532 REJ09B0397-0300 6. ROM * User Program Mode 1. Initial state The FWE assessment program that confirms that a high level has been applied to the FWE pin, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM, should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/erase control program New application program H8/3857F or H8/3854F Boot program Flash memory FWE assessment program Transfer program (RAM) SCI New application program H8/3857F or H8/3854F Boot program Flash memory FWE assessment program Transfer program Programming/erase control program Application program (old version) Application program (old version) (RAM) SCI 2. Programming/erase control program transfer When a high level is applied to the FWE pin, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program H8/3857F or H8/3854F Boot program Flash memory FWE assessment program Transfer program Programming/erase control program Flash memory erase New application program (RAM) SCI H8/3857F or H8/3854F Boot program Flash memory FWE assessment program Transfer program Programming/erase control program (RAM) SCI Program execution state Figure 6.5 User Program Mode (Example) Rev.3.00 Jul. 19, 2007 page 124 of 532 REJ09B0397-0300 6. ROM Differences between Boot Mode and User Program Mode Table 6.1 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Note: * Possible Not possible Program/program-verify User Program Mode Possible Possible Erase/erase-verify Program/program-verify To be provided by the user, in accordance with the recommended algorithm. Block Configuration: The flash memory is divided into one 12-kbyte block, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. Address H'0000 1 kbyte 1 kbyte 1 kbyte 1 kbyte 28 kbytes 16 kbytes 12 kbytes Address H'EDFF Figure 6.6 Flash Memory Blocks 6.2.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 6.2. Table 6.2 Pin Name Reset Flash write enable Test 2 Test Transmit data* Receive data* Note: * Flash Memory Pins Abbr. RES FWE TEST2 TEST TXD RXD I/O Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets H8/3857F operating mode Sets H8/3857F operating mode SCI3 transmit data output SCI3 receive data input The transmit data pin and receive data pin are used in boot mode. 60 kbytes Rev.3.00 Jul. 19, 2007 page 125 of 532 REJ09B0397-0300 6. ROM 6.2.5 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 6.3. In order to access these registers, the FLSHE bit in SYSCR3 must be set to 1. Table 6.3 Flash Memory Registers Abbr. FLMCR1* EBR*5 MDCR SYSCR3 5 Register Name Flash memory control register 1 Flash memory control register 2 Erase block register Mode control register System control register 3 R/W R/W* 2 Initial Value H'00* 3 Address H'FF80*1 H'FF81*1 H'FF83*1 H'FF89 H'FF8F FLMCR2*5 R/W*2 R/W*2 R R/W H'00*4 H'00*4 Undefined H'00 Notes: 1. Flash memory register selection is performed by means of the FLSHE bit in system control register 3 (SYSCR3). 2. When the FWE bit in FLMCR1 is cleared to 0, writes are invalid. 3. When a high level is input to the FWE pin, the initial value is H'80. 4. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 5. FLMCR1, FLMCR2, and EBR are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. The registers shown in table 6.3 are for use exclusively by the flash memory version. In the mask ROM version, a read access to the address of a register other than MDCR will always return 0, a read access to the MDCR address will return an undefined value, and writes are invalid. 6.3 6.3.1 Bit Flash Memory Register Descriptions Flash Memory Control Register 1 (FLMCR1) 7 FWE * R 6 SWE 0 R/W 5 0 4 0 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Initial value Read/Write Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the corresponding bit. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by setting SWE to 1 Rev.3.00 Jul. 19, 2007 page 126 of 532 REJ09B0397-0300 6. ROM when FWE = 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is initialized by a reset and in standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. Writes to the SWE bit in FLMCR1 are enabled only when FWE = 1; writes to the EV and PV bits only when FWE = 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1. Bit 7--Flash Write Enable (FWE): Bit 7 sets hardware protection against flash memory programming/erasing. See section 6.9, Flash Memory Programming and Erasing Precautions, for more information on the use of this bit. Bit 7: FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Bit 6--Software Write Enable (SWE)*1*2: Bit 6 enables or disables flash memory programming and erasing. (This bit should be set before setting bits ESU, PSU, EV, PV, E, P, and EB6 to EB0, and should not be cleared at the same time as these bits.) Bit 6: SWE 0 1 Description Programming/erasing disabled Programming/erasing enabled [Setting condition] When FWE = 1 (initial value) Bits 5 and 4--Reserved Bits: Bits 5 and 4 are reserved; they are always read as 0 and cannot be modified. Bit 3--Erase-Verify (EV)*1: Bit 3 selects erase-verify mode transition or clearing. (Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time.) Bit 3: EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 (initial value) Rev.3.00 Jul. 19, 2007 page 127 of 532 REJ09B0397-0300 6. ROM Bit 2--Program-Verify (PV)*1: Bit 2 selects program-verify mode transition or clearing. (Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.) Bit 2: PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 (initial value) Bit 1--Erase (E)*1*3: Bit 1 selects erase mode transition or clearing. (Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time.) Bit 1: E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 (initial value) Bit 0--Program (P)*1*3: Bit 0 selects program mode transition or clearing. (Do not set the SWE, ESU, PSU, EV, PV, or E bit at the same time.) Bit 0: P 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 (initial value) Notes: 1. Do not set multiple bits simultaneously. Do not cut VCC while a bit is set. 2. The SWE bit must not be set or cleared at the same time as other bits (bits EV, PV, E, and P in FLMCR1, and bits ESU and PSU in FLMCR2). 3. P bit and E bit setting should be carried out in accordance with the program/erase algorithms shown in section 6.5, Flash Memory Programming/Erasing. Before setting either of these bits, a watchdog timer setting should be made to prevent program runaway. See section 6.9, Flash Memory Programming and Erasing Precautions, for more information on the use of these bits. Rev.3.00 Jul. 19, 2007 page 128 of 532 REJ09B0397-0300 6. ROM 6.3.2 Bit Flash Memory Control Register 2 (FLMCR2) 7 FLER 6 0 5 0 4 0 3 0 2 0 1 ESU 0 R/W 0 PSU 0 R/W Initial value Read/Write 0 R FLMCR2 is an 8-bit register used for monitoring of flash memory program/erase protection (error protection) and for flash memory program/erase mode setup. FLMCR2 is initialized to H'00 by a reset. The ESU and PSU bits are cleared to 0 in standby mode, hardware protect mode, and software protect mode. Bit 7--Flash Memory Error (FLER): Bit 7 indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. Bit 7: FLER Description 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset 1 An error occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 6.6.3, Error Protection (initial value) Bits 6 to 2--Reserved Bits: Bits 6 to 2 are reserved; they are always read as 0 and cannot be modified. Bit 1--Erase Setup (ESU)*: Bit 1 prepares for a transition to erase mode. Set this bit to 1 before setting the E bit in FLMCR1. (Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.) Bit 1: ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1 and SWE = 1 (initial value) Rev.3.00 Jul. 19, 2007 page 129 of 532 REJ09B0397-0300 6. ROM Bit 0--Program Setup (PSU)*: Bit 0 prepares for a transition to program mode. Set this bit to 1 before setting the P bit in FLMCR1. (Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.) Bit 0: PSU 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE = 1 (initial value) Note: * Do not set multiple bits simultaneously. Do not cut VCC while a bit is set. 6.3.3 Bit Erase Block Register (EBR) 7 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W Initial value Read/Write 0 EBR is a register that specifies the flash memory erase area, block by block. Bits 6 to 0 of EBR are read/write bits. EBR is initialized to H'00 by a reset, in standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin while the SWE bit in FLMCR1 is cleared to 0. When a bit in EBR is set to 1, the corresponding block can be erased. Other blocks are erase-protected. As erasing is carried out on a block-by-block basis, only one bit in EBR should be set at a time (more than one bit must not be set). The flash memory block configuration is shown in table 6.4. To erase the entire flash memory, individual blocks must be erased in succession. Rev.3.00 Jul. 19, 2007 page 130 of 532 REJ09B0397-0300 6. ROM Table 6.4 Block (Size) Flash Memory Erase Blocks Addresses H'0000 to H'03FF H'0400 to H'07FF H'0800 to H'0BFF H'0C00 to H'0FFF H'1000 to H'7FFF H'8000 to H'BFFF H'C000 to H'EDFF EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (12 kbytes) 6.3.4 Bit Mode Control Register (MDCR) 7 6 0 5 0 4 0 3 0 2 0 1 TSDS2 * R 0 TSDS1 * R Initial value Read/Write Note: * 0 Determined by the TEST2 and TEST pins. MDCR is an 8-bit read-only register used to monitor the current operating mode of the H8/3857F. Bits 7 to 2--Reserved Bits: Bits 7 to 2 are reserved; they are always read as 0 and cannot be modified. Bits 1 and 0--Test Pin Monitor 2 and 1 (TSDS2, TSDS1): Bits 1 and 0 show values that reflect the input levels at the test pins (TEST2 and TEST) (i.e. they indicate the current operating mode). Bits TSDS2 and TSDS1 correspond to pins TEST2 and TEST, respectively. These bits are readonly, and cannot be modified. 6.3.5 Bit System Control Register 3 (SYSCR3) 7 6 0 5 0 4 0 3 FLSHE 0 R/W 2 0 1 0 0 0 Initial value Read/Write 0 SYSCR3 is an 8-bit read/write register that controls the on-chip flash memory. Rev.3.00 Jul. 19, 2007 page 131 of 532 REJ09B0397-0300 6. ROM SYSCR3 is initialized to H'00 by a reset. Bits 7 to 4--Reserved Bits: Bits 7 to 4 are reserved; they are always read as 0 and cannot be modified. Bit 3--Flash Memory Control Register Enable (FLSHE): Bit 3 controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, and EBR). When the FLSHE bit is set to 1, the flash memory control registers can be read and written to. When FLSHE is cleared to 0, the flash memory control registers are unselected. In this case, the contents of the flash memory control registers are retained. Bit 3: FLSHE Description 0 1 Flash memory control registers are unselected for addresses H'FF80 to H'FF83 (initial value) Flash memory control registers are selected for addresses H'FF80 to H'FF83 Bits 2 to 0--Reserved Bits: Bits 2 to 0 are reserved; they are always read as 0 and cannot be modified. 6.4 On-Board Programming Modes When an on-board programming mode is selected, the on-chip flash memory can be programmed, erased, and verified. There are two on-board programming modes: boot mode and user program mode. Table 6.5 shows the pin settings for transition to each mode. A state transition diagram for flash memory related modes is shown in figure 6.3. Table 6.5 Mode MCU Mode Boot mode User program mode* 1 On-Board Programming Mode Selection Pins FWE 1* 1 2 TEST2 0 1 TEST 0 0 Notes: 1. The FWE pin should normally be set to 0. Before performing programming, erasing, or verifying, set the FWE pin to 1 and make a transition to user program mode. 2. For the high level application timing, see items (f) and (g) under (3) Notes on Use of Boot Mode in section 6.4.1, Boot Mode. Rev.3.00 Jul. 19, 2007 page 132 of 532 REJ09B0397-0300 6. ROM 6.4.1 Boot Mode To use boot mode, a user program for programming and erasing the flash memory must be provided in advance in the host. SCI3 is used in asynchronous mode. When a reset start is executed after the chip's pins have been set to boot mode, the built-in boot program is activated, and the programming control program provided in the host is transferred sequentially to the chip using SCI3. The chip writes the programming control program received via SCI3 to the programming control program area in the on-chip RAM. After the transfer is completed, execution branches to the start address (H'FB80) of the programming control program area, and the programming control program execution state is entered (flash memory programming is performed). Therefore, a routine conforming to the programming algorithm described later must be provided in the programming control program transferred from the host. Figure 6.7 shows the system configuration in boot mode, and figure 6.8 shows the boot mode execution procedure. H8/3857F H8/3854F Flash memory Host Reception of programming data RXD Transmission of verify data TXD SCI3 On-chip RAM Figure 6.7 System Configuration when Using Boot Mode Rev.3.00 Jul. 19, 2007 page 133 of 532 REJ09B0397-0300 6. ROM Start Set pins to boot mode and execute reset start Host transmits data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No n + 1 n n=N? Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA byte to host Execute programming control program transferred to on-chip RAM Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 6.8 Boot Mode Execution Procedure Rev.3.00 Jul. 19, 2007 page 134 of 532 REJ09B0397-0300 6. ROM Automatic SCI Bit Rate Adjustment Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 6.9 RXD Input Signal in Automatic SCI Bit Rate Adjustment When boot mode is initiated, the chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host . The SCI transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the chip's system clock frequency, there will be a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the host's transfer bit rate should be set to 2400, 4800, or 9600 bps*1. Table 6.6 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the chip's bit rate is possible. The boot program should be executed within this system clock oscillation frequency range*2. Notes: 1. Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be used. 2. Although the chip may also perform automatic bit rate adjustment with bit rate and system clock combinations other than those shown in table 6.6, a degree of error will arise between the bit rates of the host and the chip, and subsequent transfer will not be performed normally. Therefore, only a combination of bit rate and system clock oscillation frequency within one of the ranges shown in table 6.6 can be used for boot mode execution. Rev.3.00 Jul. 19, 2007 page 135 of 532 REJ09B0397-0300 6. ROM Table 6.6 System Clock Oscillation Frequencies for which Automatic Adjustment of Chip's Bit Rate is Possible System Clock Oscillation Frequencies (fosc) for which Automatic Adjustment Host Bit Rate of Chip's Bit Rate is Possible 9600bps 4800bps 2400bps 1.2288 MHz, 2.4576 MHz, 4.9152 MHz, 6 MHz to 10 MHz 1.2288 MHz, 2.4576 MHz, 4 MHz to 10 MHz 1.2288 MHz, 2 MHz to 10 MHz On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 1-kbyte area from H'F780 to H'FB7F is reserved as an area for use by the boot program, as shown in figure 6.10. The area to which the programming control program is transferred comprises addresses H'FB80 to H'FF7F. The boot program area becomes available when the programming control program transferred to RAM switches to the execution state. A stack area should be set up as necessary. H'F780 Boot program area* H'FB7F H'FB80 Programming control program area H'FF7F Note: * The boot program area cannot be used until the programming control program transferred to RAM switches to the execution state. Note also that the boot program remains in this area in RAM even after control branches to the programming control program. Figure 6.10 RAM Areas in Boot Mode Rev.3.00 Jul. 19, 2007 page 136 of 532 REJ09B0397-0300 6. ROM Notes on Use of Boot Mode 1. When the chip comes out of reset in boot mode, it measures the low period of the input at the SCI3's RXD pin. The reset should end with RXD high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the RXD input. 2. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 3. Interrupts cannot be used while the flash memory is being programmed or erased. 4. The RXD and TXD lines should be pulled up on the board. 5. Before branching to the programming control program (RAM area address H'FB80), the chip terminates transmit and receive operations by the on-chip SCI3 (by clearing the RE and TE bits to 0 in SCR3), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TXD, goes to the high-level output state (PCR42 = 1 in port control register 4, P42 = 1 in port data register 4). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. 6. Boot mode can be entered by making the pin settings shown in table 6.5, and then executing a reset start. Boot mode can be exited by waiting at least 10 system clock cycles after driving the reset pin low*2, then setting the FWE, TEST2, and TEST pins to execute reset release*1. Boot mode can also be exited when a WDT overflow reset occurs. Do not change the input levels at the FWE, TEST2, and TEST pins while in boot mode. The FWE pin must not be driven low while the boot program is running or flash memory is being programmed or erased*3. 7. If the input level of the TEST2, TEST, or FWE pin is changed (for example, from low to high) during a reset, the MCU's operating mode will change, and as a result, the port states will also change. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the MCU. Notes: 1. TEST2, TEST, and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. See section 3.2.2, Reset Sequence, and section 6.9, Flash Memory Programming and Erasing Precautions. Rev.3.00 Jul. 19, 2007 page 137 of 532 REJ09B0397-0300 6. ROM 3. For further information on FWE application and disconnection, see section 6.9, Flash Memory Programming and Erasing Precautions. 6.4.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user programming/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and incorporating a programming/erase control program in part of the program area as necessary. To select user program mode, start up in user program mode (TEST2 = 1, TEST = 0), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in user mode. The flash memory itself cannot be read while the SWE bit is set to 1 to carry out flash memory programming or erasing, so the control program that performs programming and erasing must be executed in on-chip RAM. Rev.3.00 Jul. 19, 2007 page 138 of 532 REJ09B0397-0300 6. ROM Figure 6.11 shows the execution procedure when the programming/erase control program is transferred to on-chip RAM. Write FWE assessment program and transfer program (and programming/erase control program if necessary) beforehand TEST2 = 1, TEST = 0 Reset start Transfer programming/erase control program to RAM Branch to programming/erase control program in RAM area FWE = high* Execute programming/erase control program in RAM (flash memory rewriting) Release FWE* Branch to application program in flash memory Notes: Do not apply a constant high level to the FWE pin. A high level should be applied to the FWE pin only when programming or erasing flash memory. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 6.9, Flash Memory Programming and Erasing Precautions. Figure 6.11 User Program Mode Execution Procedure Rev.3.00 Jul. 19, 2007 page 139 of 532 REJ09B0397-0300 6. ROM 6.5 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be placed in on-chip RAM, and executed there. See section 6.9, Flash Memory Programming and Erasing Precautions, for points to note concerning programming and erasing, and section 15.2.6, Flash Memory Characteristics, for the wait times after setting or clearing FLMCR1 and FLMCR2 bits. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in FLMCR1 and the ESU and PSU bits in FLMCR2 is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming should be performed in the erased state. Do not perform additional programming on addresses that have already been programmed. 6.5.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 6.12 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing programming data reliability. Programming should be carried out 32 bytes at a time. The wait times (x, y, z, , , , , ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and flash memory control register 2 (FLMCR2), and the maximum number of programming operations (N), are shown in table 15.10 in section 15.2.6, Flash Memory Characteristics. Following the elapse of (x) s or more after the SWE bit is set to 1 in FLMCR1, 32-byte programming data is stored in the programming data area and the reprogramming data area, and the 32 bytes of data in the reprogramming data area in RAM are written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The programming address and programming data are latched in the flash memory. A 32-byte data transfer must be Rev.3.00 Jul. 19, 2007 page 140 of 532 REJ09B0397-0300 6. ROM performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z + + ) s as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) s. 6.5.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least () s later). The watchdog timer is cleared following the elapse of more than (y + z + + ) s after being set, and the operating mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogramming data is computed (see figure 6.12) and transferred to the reprogramming data area. After 32 bytes of data have been verified, exit program-verify mode, wait for at least () s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Note: A 32-byte area for storing programming data and a 32-byte area for storing reprogramming data must be provided in RAM. Rev.3.00 Jul. 19, 2007 page 141 of 532 REJ09B0397-0300 6. ROM START *1 Set SWE bit in FLMCR1 Wait (x) s *6 *5 Store 32-byte programming data in programming data area and reprogramming data area n=1 m=0 Consecutively write 32-byte data in repro2 gramming data area in RAM to flash memory * Enable WDT Set PSU bit in FLMCR2 Wait (y) s Set P bit in FLMCR1 Wait (z) s Clear P bit in FLMCR1 Wait () s Clear PSU bit in FLMCR2 Wait () s Disable WDT Set PV bit in FLMCR1 Wait () s H'FF dummy write to verify address Wait () s Read verify data Increment address Programming data = verify data? Yes Reprogramming data computation No *6 Start of programming *6 End of programming *6 nn+1 *6 *6 *6 *3 m=1 *4 Transfer reprogramming data to reprogramming data area *5 32-byte data verification completed? Yes Clear PV bit in FLMCR1 Wait () s m = 0? Yes Clear SWE bit in FLMCR1 End of programming No No RAM Programming data storage area (32 bytes) Reprogramming data storage area (32 bytes) *6 *6 n N? Yes Clear SWE bit in FLMCR1 Programming failure No Notes: 1. Programming should be performed in the erased state. Do not perform additional programming on addresses that have already been programmed. (Perform 32-byte programming on memory after all 32 bytes have been erased.) 2. Data transfer is performed by byte transfer (word transfer is not possible). The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. 3. Verify data is read in 16-bit (word) units. 4. Reprogramming data is determined by the operation shown in the table below (comparison between the data stored in the programming data area and the verify data). Bits for which the reprogramming data is 0 are programmed in the next programming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is No. 5. A 32-byte area for storing programming data and a 32-byte area for storing reprogramming data must be provided in RAM. The contents of the latter are rewritten in accordance with reprogramming data computation. 6. The values of x, y, z, , , , , , and N are shown in section 15.2.6, Flash Memory Characteristics. Programming Data 0 0 1 1 Verify Data 0 1 0 1 Reprogramming Data 1 0 1 1 Comments Programmed bits are not reprogrammed Programming incomplete; reprogram Still in erased state; no action Note: The memory erased state is "1". Programming is performed on "0" reprogramming data. Figure 6.12 Program/Program-Verify Flowchart Rev.3.00 Jul. 19, 2007 page 142 of 532 REJ09B0397-0300 6. ROM 6.5.3 Erase Mode To erase an individual flash memory block, follow the erase/erase-verify flowchart (single-block erase) shown in figure 6.13. The wait times (x, y, z, , , , , ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and flash memory control register 2 (FLMCR2), and the maximum number of erase operations (N), are shown in table 15.10 in section 15.2.6, Flash Memory Characteristics. To perform data or program erasure, make a 1-bit setting for the flash memory area to be erased in the erase block register (EBR) at least (x) s after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, set up the watchdog timer to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + + ) s as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, prewriting (setting memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 6.5.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the ESU bit in FLMCR2 is cleared at least () s later). The watchdog timer is cleared following the elapse of more than (y + z + + ) s after being set, and the operating mode is switched to eraseverify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (y) s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. If the read data has been erased (all 1), execute a dummy write to the next address, and perform an erase-verify. If the read data has not been erased, select erase mode again and repeat the erase/erase-verify sequence as before. However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for at least () s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1-bit setting in EBR for the flash memory block to be erased, and repeat the erase/erase-verify sequence as before. Rev.3.00 Jul. 19, 2007 page 143 of 532 REJ09B0397-0300 6. ROM START *1 Set SWE bit in FLMCR1 Wait (x) s n=1 Set EBR Enable WDT Set ESU bit in FLMCR2 Wait (y) s Set E bit in FLMCR1 Wait (z) ms Clear E bit in FLMCR1 Wait () s Clear ESU bit in FLMCR2 Wait () s Disable WDT Set EV bit in FLMCR1 Wait () s Set block start address as verify address H'FF dummy write to verify address Wait () s Read verify data Increment address Verify data = all 1? Yes No Last address of block? Yes Clear EV bit in FLMCR1 Wait () s Clear EV bit in FLMCR1 Wait () s No *2 *4 *2 Start of erase *2 Erase halted *2 *2 *2 nn+1 *2 *3 *2 No *5 *2 *2 n N? Yes Clear SWE bit in FLMCR1 Erase failure No End of erasing of all erase blocks? Yes Clear SWE bit in FLMCR1 End of erasing Notes: 1. 2. 3. 4. 5. Prewriting (setting erase block data to all 1) is not necessary. The values of x, y, z, , , , , , and N are shown in section 15.2.6, Flash Memory Characteristics. Verify data is read in 16-bit (word) units. Set only one bit in EBR; two or more bits must not be set. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. Figure 6.13 Erase/Erase-Verify Flowchart (Single-Block Erase) Rev.3.00 Jul. 19, 2007 page 144 of 532 REJ09B0397-0300 6. ROM 6.6 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 6.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. In this state, the settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the erase block register (EBR) are reset. (See table 6.7.) Table 6.7 Hardware Protection Functions Item FWE pin protection Description * When a low level is input to the FWE pin, FLMCR1, FLMCR2 (except the FLER bit), and EBR are initialized, and the 3 program/erase-protected state is entered.* In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, and EBR are initialized, and the program/ erase-protected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low for a minimum of 40 ms (oscillation 4 stabilization time)* after powering on. In the case of a reset during operation, hold the RES pin low for a minimum of 10 system clock cycles (10). Program Erase Not possible Verify*1 Not Not possible*2 possible Reset/standby * protection Not possible Not Not 2 possible* possible * Notes: 1. 2. 3. 4. Two modes: program-verify and erase-verify. All blocks are unerasable and block-by-block specification is not possible. For details see section 6.9, Flash Memory Programming and Erasing Precautions. For details see the AC characteristics in sections 15.2.3 and 16.2.3, Electrical Characteristics. Rev.3.00 Jul. 19, 2007 page 145 of 532 REJ09B0397-0300 6. ROM 6.6.2 Software Protection Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), and the erase block register (EBR). With software protection, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. (See table 6.8.) Table 6.8 Software Protection Functions Item SWE bit protection Block protection Description * Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM.) Individual blocks can be protected from erasing and programming by settings in the erase block register (EBR)*2. If H'00 is set in EBR, all blocks are protected from erasing and programming. Program Erase Not possible Not possible Not possible Verify*1 Not possible Possible * * Notes: 1. Two modes: program-verify and erase-verify. 2. When not erasing, clear all EBR bits to 0. 6.6.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing*1, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. FLMCR1, FLMCR2, and EBR settings*2 are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: 1. When flash memory is read*3 during programming/erasing (including a vector read or instruction fetch) 2. Immediately after the start of exception handling (excluding a reset) during programming/erasing*4 Rev.3.00 Jul. 19, 2007 page 146 of 532 REJ09B0397-0300 6. ROM 3. When a SLEEP instruction (including software standby) is executed during programming/erasing Error protection is released only by a reset. Figure 6.14 shows the flash memory state transition diagram. Notes: 1. This is the state in which the P bit or E bit is set to 1 in FLMCR1. 2. FLMCR1, FLMCR2, and EBR can be written to. However, registers will be initialized if a transition is made to software standby mode in the error protection state. 3. The read value is undefined. 4. Before exception handling stack and vector read operations are performed. Reset (hardware protection) RD VF PR ER FLER = 0 Program mode Erase mode RD VF PR ER FLER = 0 Er (so ror o ftw cc ar urr e s en tan ce db y) RES = 0 Error occurrence S RE =0 RES = 0 FLMCR1, FLMCR2, and EBR initialized Error protect mode RD VF PR ER FLER = 1 Standby mode Standby mode release Error protect mode (standby mode) RD VF PR ER INIT FLER = 1 FLMCR1, FLMCR2 (except FLER bit), and EBR initialized Legend: RD : Memory read possible VF : Verify-read possible PR : Programming possible ER : Erasing possible RD VF PR ER INIT : Memory read not possible : Verify-read not possible : Programming not possible : Erasing not possible : Register (FLMCR1, FLMCR2, EBR) initialization state Figure 6.14 Flash Memory State Transitions The error protection function is invalid for abnormal operations other than the FLER bit setting conditions. Also, if a certain time has elapsed before this protection state is entered, damage may already have been caused to the flash memory. Consequently, this function cannot provide complete protection against damage to flash memory. Rev.3.00 Jul. 19, 2007 page 147 of 532 REJ09B0397-0300 6. ROM To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied, and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog timer or other means. There may also be cases where the flash memory is in an erroneous programming or erroneous erasing state at the point of transition to the protect mode, or where programming or erasing is not properly carried out because of an abort. In cases such as these, a forced recovery (program rewrite) must be executed using boot mode. However, it may also happen that boot mode cannot be normally initiated because of overprogramming or overerasing. 6.7 Interrupt Handling during Flash Memory Programming and Erasing All interrupts should be disabled when flash memory is being programmed or erased (while the P or E bit is set in FLMCR1) and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt occurrence during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, there are conditions for disabling interrupts in the on-board programming modes alone, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All interrupt requests must therefore be disabled inside and outside the MCU when flash memory is programmed or erased. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until programming by the programming control program has been completed. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undefined values will be returned). * If a value has not yet been written in the interrupt vector table, interrupt exception handling will not be executed correctly. Rev.3.00 Jul. 19, 2007 page 148 of 532 REJ09B0397-0300 6. ROM 6.8 6.8.1 Flash Memory Writer Mode Writer Mode Setting Programs and data can be written and erased in Writer mode as well as in the on-board programming modes. In Writer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas Technology microcomputer device type with 64-kbyte onchip flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. 6.8.2 Socket Adapter and Memory Map In Writer mode, a socket adapter for the relevant kind of package is attached to the PROM programmer. The socket adapter performs 144-pin to 32-pin conversion for the HD64F3857, and 100-pin to 32-pin conversion for the HD64F3854. The socket adaptor ptoduct code is given in table 6.9. Figure 6.15 shows the memory map in Writer mode, and figures 6.16 (a) and (b) show the socket adapter pin interconnections for the HD64F3857 and the HD64F3854. Table 6.9 Part No. HD64F3857 HD64F3854 Socket Adapter Part No. Package 144-pin TQFP (TFP-144) 144-pin QFP (FP-144H) 100-pin TQFP (TFP-100G) 100-pin QFP (FP-100B) Socket Adapter Part No. Details available from Renesas Sales Rev.3.00 Jul. 19, 2007 page 149 of 532 REJ09B0397-0300 6. ROM HD64F3857 HD64F3854 MCU mode H'0000 Writer mode H'0000 On-chip ROM area H'EDFF H'EDFF Undefined values output H'1FFFF Figure 6.15 Memory Map in Writer Mode Rev.3.00 Jul. 19, 2007 page 150 of 532 REJ09B0397-0300 6. ROM Socket Adapter (32-Pin Conversion) FWE P20 P21 P22 P23 P24 P25 P26 P27 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG23 SEG22 SEG21 VCC AVCC TEST X1 P54 PB5 PB6 Vci VLCD VSS AVSS TEST2 PB4 RES OSC1 OSC2 NC (OPEN) Power-on reset circuit Oscillation circuit NC (OPEN) Legend: FWE FO7 to FO0 FA15 to FA0 OE CE WE 2, 30 VSS 16 HD64F3857 FP-144H, TFP-144 36 16 15 14 13 12 11 10 9 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 75 74 73 34 17 32 28 4 23 24 117 123 29, 124 26 33 22 35 31 30 Other pins Pin Name HN28F101P (32 Pins) Pin No. Pin Name FWE FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FA8 FA9 FA10 FA11 FA12 FA13 FA14 FA15 CE OE WE VCC 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 22 24 31 32 : Flash write enable : Data input/output : Address input : Output enable : Chip enable : Write enable Figure 6.16 (a) HD64F3857 Socket Adapter Pin Interconnections Rev.3.00 Jul. 19, 2007 page 151 of 532 REJ09B0397-0300 6. ROM Socket Adapter (32-Pin Conversion) Pin Name FWE P20 P21 P22 P23 P24 P25 P26 P27 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG23 SEG22 SEG21 VCC TEST X1 P54 PB5 PB6 VSS TEST2 PB4 RES OSC1 OSC2 Power-on reset circuit Oscillation circuit NC (OPEN) Legend: FWE FO7 to FO0 FA15 to FA0 OE CE WE 2, 30 VSS 16 HD64F3854 FP-100B, TFP-100G 25 15 14 13 12 11 10 9 8 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 68 67 66 23 22 18 3 27 28 19 16 26 24 21 20 HN28F101P (32 Pins) Pin Name FWE FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FA8 FA9 FA10 FA11 FA12 FA13 FA14 FA15 CE OE WE VCC Pin No. 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 22 24 31 32 : Flash write enable : Data input/output : Address input : Output enable : Chip enable : Write enable Figure 6.16 (b) HD64F3854 Socket Adapter Pin Interconnections Rev.3.00 Jul. 19, 2007 page 152 of 532 REJ09B0397-0300 6. ROM 6.8.3 Writer Mode Operation Table 6.10 shows how the different operating modes are set when using Writer mode, and table 6.11 lists the commands used in Writer mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the FO7 signal. In status read mode, error information is output if an error occurs. Table 6.10 Settings for Operating Modes In Writer Mode Pin Names*4 Mode Read Output disable Command write Chip disable*1 FWE H/L H/L H/L* H/L 3 CE L L L H OE L H H X WE H H L X FO0 to FO7 Data output Hi-Z Data input Hi-Z FA0 to FA15 Ain X Ain*2 X Legend: L: Low level H: High level X: Undefined Hi-Z: High impedance Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes in auto-program and auto-erase modes, input a high level to the FWE pin. 4. Pin names are those assigned in Writer mode. See figure 6.16 (a) for the H8/3857F, and figure 6.16 (b) for the H8/3854F. Rev.3.00 Jul. 19, 2007 page 153 of 532 REJ09B0397-0300 6. ROM Table 6.11 Writer Mode Commands Number of Cycles 1+n 129 2 3 1st Cycle Mode write write write write Address X X X X Data H'00 H'40 H'20 H'71 Mode read write write write 2nd Cycle Address RA WA X X Data Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Legend: RA: Read address WA: Programming address Dout: Read data Din: Programming data Notes: 1. In auto-program mode, 129 cycles are required for command writing by means of a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 6.8.4 Memory Read Mode 1. After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. 2. Command writes can be performed in memory read mode, just as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After power-on, memory read mode is entered. 5. Do not make a setting outside the valid address range. Rev.3.00 Jul. 19, 2007 page 154 of 532 REJ09B0397-0300 6. ROM Table 6.12 AC Characteristics in Memory Read Mode (1) (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 Max 30 30 Unit s ns ns ns ns ns ns ns Notes Command write ADDRESS Memory read mode ADDRESS STABLE CE OE WE DATA twep tceh tnxtc tces tf H'00 tdh tds tr DATA Note: Data is latched on the rising edge of WE. Figure 6.17 Timing Waveforms for Memory Read after Command Write Rev.3.00 Jul. 19, 2007 page 155 of 532 REJ09B0397-0300 6. ROM Table 6.13 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 Max 30 30 Unit s ns ns ns ns ns ns ns Notes XX mode command write ADDRESS ADDRESS STABLE CE OE WE DATA DATA tnxtc tces tf twep tceh tr H'XX tdh tds Note: Do not enable WE and OE simultaneously. Figure 6.18 Timing Waveforms in Transition from Memory Read Mode to Another Mode Rev.3.00 Jul. 19, 2007 page 156 of 532 REJ09B0397-0300 6. ROM Table 6.14 AC Characteristics in Memory Read Mode (2) (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh Min 5 Max 20 150 150 100 Unit s ns ns ns ns Notes ADDRESS ADDRESS STABLE ADDRESS STABLE CE OE WE tacc DATA DATA toh DATA toh tacc VIL VIL VIH Figure 6.19 Timing Waveforms for CE, OE Enable State Read ADDRESS ADDRESS STABLE ADDRESS STABLE tacc CE OE WE DATA tce toe tdf DATA toh tce toe VIH tdf DATA toh tacc Figure 6.20 Timing Waveforms for CE, OE Clocked Read Rev.3.00 Jul. 19, 2007 page 157 of 532 REJ09B0397-0300 6. ROM 6.8.5 Auto-Program Mode AC Characteristics Table 6.15 AC Characteristics in Auto-Program Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time WE rise time WE fall time Write setup time Write end setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tr tf tpns tpnh Min 20 0 0 50 50 70 1 0 60 1 100 100 Max 150 3000 30 30 Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns Notes Rev.3.00 Jul. 19, 2007 page 158 of 532 REJ09B0397-0300 6. ROM FWE ADDRESS CE OE WE FO7 tpns ADDRESS STABLE tceh tnxtc twep tces tf tds tdh tr tas tah tpnh tnxtc Data transfer 1 byte ... 128 bytes twsts tspa twrite (1 to 3000ms) Programming operation end identification signal FO6 Programming normal end identification signal Programming wait DATA H'40 DATA DATA FO0 to 5= 0 Figure 6.21 Auto-Program Mode Timing Waveforms Notes on Use of Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than a valid address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 6.20). Do not perform transfer after the second cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-programming operation for a 128-byte block for each address. Characteristics cannot be guaranteed for two or more programming operations. 7. Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode can also be used for this purpose (the FO7 status polling pin is used to identify the end of an auto-program operation). 8. Status polling FO6 and FO7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Rev.3.00 Jul. 19, 2007 page 159 of 532 REJ09B0397-0300 6. ROM 6.8.6 Auto-Erase Mode AC Characteristics Table 6.16 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time WE rise time WE fall time Erase setup time Erase end setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tr tf tens tenh Min 20 0 0 50 50 70 1 100 100 100 Max 150 40000 30 30 Unit s ns ns ns ns ns ms ns ms ns ns ns ns Notes FWE tens ADDRESS tenh CE OE WE FO7 FO6 tces tceh tspa tnxtc twep tests terase (100 to 40000ms) Erase end identification signal Erase normal end confirmation signal tf tds tr tdh tnxtc CLin DATA H'20 DLin H'20 FO0 to 5= 0 Figure 6.22 Auto-Erase Mode Timing Waveforms Rev.3.00 Jul. 19, 2007 page 160 of 532 REJ09B0397-0300 6. ROM Notes on Use of Auto-Erase Mode 1. Auto-erase mode supports only total memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (the FO7 status polling pin is used to identify the end of an auto-erase operation). 4. Status polling FO6 and FO7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. 6.8.7 Status Read Mode 1. Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write for other than status read mode is performed. Table 6.17 AC Characteristics in Status Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 Max 150 100 150 30 30 Unit s ns ns ns ns ns ns ns ns ns ns Notes Rev.3.00 Jul. 19, 2007 page 161 of 532 REJ09B0397-0300 6. ROM ADDRESS CE tce OE WE tces tf tds twep tceh tr tdh DATA H'71 tnxtc tces tf tds H'71 twep tceh tr tdh DATA tnxtc toe tdf tnxtc Note: FO2 and FO3 are undefined. Figure 6.23 Status Read Mode Timing Waveforms Table 6.18 Status Read Mode Return Codes Pin Name Attribute FO7 Normal end identification FO6 Command error 0 FO5 Programming error 0 Programming error: 1 Otherwise: 0 FO4 Erase error FO3 FO2 FO1 FO0 Programming Valid address or erase count error exceeded 0 Count exceeded: 1 Otherwise: 0 0 Valid address error: 1 Otherwise: 0 Initial value 0 Indications 0 Erase error: 1 Otherwise: 0 0 0 Normal end: 0 Command Abnormal error: 1 end: 1 Otherwise: 0 Note: FO2 and FO3 are undefined. 6.8.8 Status Polling 1. The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. 2. The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 6.19 Status Polling Output Truth Table Pin Names FO7 FO6 FO0 to FO5 Internal Operation in Progress 0 0 0 Abnormal End 1 0 0 Normal Status Indication 0 1 0 Normal End 1 1 0 Rev.3.00 Jul. 19, 2007 page 162 of 532 REJ09B0397-0300 6. ROM 6.8.9 Writer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the Writer mode setup period. A transition is made to memory read mode after the Writer mode setup time. Table 6.20 Stipulated Transition Times to Command Wait State Item Standby release (oscillation stabilization time) Writer mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 40 10 0 Max Unit ms ms ms Notes VCC RES FWE tosc1 tbmv Memory read mode command wait state Auto-program mode Auto-erase mode tdwn Command Don't care wait state Normal/abnormal end determination Don't care Command acceptance Note: When not in auto-program mode or auto-erase mode, the FWE input pin should be driven low. Figure 6.24 Oscillation Stabilization Time, Writer Mode Setup, and Power-Down Sequence 6.8.10 Notes on Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using a PROM programmer on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on a particular address block. Rev.3.00 Jul. 19, 2007 page 163 of 532 REJ09B0397-0300 6. ROM 6.9 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode and Writer mode are summarized below. 1. Use the specified voltages and timing for programming and erasing. Applying a voltage in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with 64-kbyte on-chip flash memory. Do not select the HN28F101 setting for the PROM programmer, and only use the specified socket adapter. Incorrect use may damage the device. 2. Powering on and off Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. Failure to do so may result in overprogramming or overerasing due to MCU runaway, and loss of normal memory cell operation. 3. FWE application/disconnection FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: a. Apply FWE when the VCC voltage has stabilized within its rated voltage range. b. Apply FWE when oscillation has stabilized (after the elapse of the oscillation stabilization time). c. In boot mode, apply and disconnect FWE during a reset. d. In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during program execution in flash memory. e. Do not apply FWE if program runaway has occurred. f. Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 and FLMCR2 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. Rev.3.00 Jul. 19, 2007 page 164 of 532 REJ09B0397-0300 6. ROM 4. Do not apply a constant high level to the FWE pin To prevent erroneous programming or erasing due to program runaway, etc., apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 5. Use the recommended algorithm when programming and erasing flash memory The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. 6. Do not set or clear the SWE bit during program execution in flash memory Clear the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). 7. Do not use interrupts while flash memory is being programmed or erased All interrupt requests should be disabled during FWE application to give priority to program/erase operations. 8. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 32-byte programming unit block. In Writer mode, perform only one programming operation on a 128byte programming unit block. Programming should be carried out with the entire programming unit block erased. 9. Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. 10. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. Rev.3.00 Jul. 19, 2007 page 165 of 532 REJ09B0397-0300 6. ROM 6.10 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions Please note the following when converting the F-ZTAT application software to the mask-ROM versions. The values read from the internal registers for the flash ROM or the mask-ROM version and F-ZTAT version differ as follows. Status Register FLMCR1 Bit FWE F-ZTAT Version 0: Application software running 1: Programming Mask-ROM Version 0: Application software running 1: (Not read) Note: This difference applies to all the F-ZTAT versions and all the mask-ROM versions that have different ROM size. Rev.3.00 Jul. 19, 2007 page 166 of 532 REJ09B0397-0300 7. RAM Section 7 RAM 7.1 Overview The H8/3857 Group and the H8/3854 flash memory version have 2 kbytes of high-speed on-chip static RAM, and the H8/3854 Group mask ROM version has 1 kbyte. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. Note that the H8/3854 flash memory and mask ROM versions have different ROM and RAM sizes. 7.1.1 Block Diagram Figure 7.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'F780* H'F782 H'F780 H'F782 H'F781 H'F783 On-chip RAM H'FF7E H'FF7E Even-numbered address H'FF7F Odd-numbered address Note: * This is the start address for 2-kbyte RAM. With 1-kbyte RAM, the start address is H'FB80 and the RAM area is from H'FB80 to H'FF7E. Figure 7.1 RAM Block Diagram Rev.3.00 Jul. 19, 2007 page 167 of 532 REJ09B0397-0300 7. RAM Rev.3.00 Jul. 19, 2007 page 168 of 532 REJ09B0397-0300 8. I/O Ports Section 8 I/O Ports 8.1 Overview The H8/3857 Group is provided with four 8-bit I/O ports, one 3-bit I/O port, one 8-bit input-only port, and one 1-bit input-only port. The H8/3854 Group is provided with two 8-bit I/O ports, one 3-bit I/O port, one 5-bit I/O port, one 4-bit input-only port, and one 1-bit input-only port. In addition, both group have an I/O port capable of interfacing with the on-chip LCD controller. H8/3857 Group port functions are listed in table 8.1 (a), and H8/3854 Group port functions in table 8.1 (b). Each port has a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be assigned to individual bits. See section 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions to write data in PCR or PDR. Block diagrams of each port are given in appendix C, I/O Port Block Diagrams. Rev.3.00 Jul. 19, 2007 page 169 of 532 REJ09B0397-0300 8. I/O Ports Table 8.1 (a) H8/3857 Group Port Functions Function Switching Register PMR1 TCRF, TMC, TMB PMR1 Port Port 1 Description * 8-bit I/O port * Input pull-up MOS option Pins P17 to P15/ IRQ3 to IRQ1/ TMIF, TMIC, TMIB P14/PWM P13 Other Functions External interrupts 3 to 1 Timer event input TMIF, TMIC, TMIB 14-bit PWM output None P12, P11/ Timer F output compare TMOFH, TMOFL P10/TMOW Port 2 * 8-bit I/O port * Open drain output option * High-current port Port 3 * 8-bit I/O port P27 to P22 P21/UD P20/IRQ4/ ADTRG P37 to P33 P32/SO1 P31/SI1 P30/SCK1 External interrupt 0 SCI3 data output (TXD), data input (RXD), clock input/output (SCK3) Wakeup input (WKP7 to WKP0) Timer A clock output None Timer C count-up/down selection External interrupt 4 and A/D converter external trigger None SCI1 data output (SO1), data input (SI1), clock input/output (SCK1) PMR1 PMR1 PMR2 PMR2 AMR * Input pull-up MOS option * High-current port Port 4 * 3-bit I/O port PMR3 * 1-bit input-only port P43/IRQ0 P42/TXD P41/RXD P40/SCK3 PMR2 SCR3 SMR PMR5 Port 5 * 8-bit I/O port * Input pull-up MOS option P57 to P50/ WKP7 to WKP0 Port 9* * 8-bit I/O port Port A* * 4-bit I/O port Port B Note: * 8-bit input port * P97 to P90 PA3 to PA0 PB7 to PB0/ AN7 to AN0 None None A/D converter analog input AMR This I/O port is used to interface to the LCD controller. Rev.3.00 Jul. 19, 2007 page 170 of 532 REJ09B0397-0300 8. I/O Ports Table 8.1 (b) H8/3854 Group Port Functions Function Switching Register PMR1 TCRF, TMB PMR1 PMR1 Port Port 1 Description * 5-bit I/O port * Input pull-up MOS option Pins P17, P15/ IRQ3, IRQ1/ TMIF, TMIB Other Functions External interrupts 3, 1 Timer event input TMIF, TMIB P12, P11/ Timer F output compare TMOFH, TMOFL P10/TMOW Port 2 * 8-bit I/O port * Open drain output option * High-current port Port 4 * 1-bit input-only port P43/IRQ0 * 3-bit I/O port P42/TXD P41/RXD P40/SCK3 Port 5 * 8-bit I/O port * Input pull-up MOS option Port 9* * 8-bit I/O port Port A* * 4-bit I/O port Port B Note: * 4-bit input port * P57 to P50/ WKP7 to WKP0 Wakeup input (WKP7 to WKP0) External interrupt 0 SCI3 data output (TXD), data input (RXD), clock input/output (SCK3) P27 to P21 P20/IRQ4/ ADTRG Timer A clock output None External interrupt 4 and A/D converter external trigger PMR2 AMR PMR2 SCR3 SMR PMR5 P97 to P90 PA3 to PA0 PB7 to PB4/ AN7 to AN4 None None A/D converter analog input AMR This I/O port is used to interface to the LCD controller. Rev.3.00 Jul. 19, 2007 page 171 of 532 REJ09B0397-0300 8. I/O Ports 8.2 Port 1 Some port 1 functions differ between the H8/3857 Group and the H8/3854 Group. The P16/IRQ2/TMIC, P14/PWM, and P13 pins are provided only in the H8/3857 Group, and not in the H8/3854 Group. 8.2.1 Overview Port 1 is an 8-bit I/O port. The H8/3857 Group port 1 pin configuration is shown in figure 8.1 (a), and the H8/3854 Group port 1 pin configuration in figure 8.1 (b). P1 7 /IRQ 3 /TMIF P1 6 /IRQ 2 /TMIC P1 5 /IRQ 1 /TMIB Port 1 P1 4 /PWM P1 3 P1 2 /TMOFH P1 1 /TMOFL P1 0 /TMOW Figure 8.1 (a) H8/3857 Group Port 1 Pin Configuration P17/IRQ3/TMIF P15/IRQ1/TMIB Port 1 P12/TMOFH P11/TMOFL P10/TMOW Figure 8.1 (b) H8/3854 Group Port 1 Pin Configuration Rev.3.00 Jul. 19, 2007 page 172 of 532 REJ09B0397-0300 8. I/O Ports 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Name Port data register 1 Port control register 1 Port pull-up control register 1 Port mode register 1 Port 1 Registers Abbr. PDR1 PCR1 PUCR1 PMR1 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD4 H'FFE4 H'FFE0 H'FFC8 Port Data Register 1 (PDR1) PDR1 is an 8-bit register that stores data for pins P17 through P10. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Upon reset, PDR1 is initialized to H'00 (H8/3857 Group) or H'58 (H8/3854 Group). H8/3857 Group Bit 7 P17 Initial value Read/Write H8/3854 Group Bit 7 P17 Initial value Read/Write 0 R/W 6 1 5 P15 0 R/W 4 1 3 1 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W In the H8/3854 Group, bits 6, 4, and 3 are reserved, and must always be set to 1. Rev.3.00 Jul. 19, 2007 page 173 of 532 REJ09B0397-0300 8. I/O Ports Port Control Register 1 (PCR1) PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17 to P10 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin. Upon reset, PCR1 is initialized to H'00. PCR1 is a write-only register. All bits are read as 1. H8/3857 Group Bit 7 PCR17 Initial value Read/Write H8/3854 Group Bit 7 PCR17 Initial value Read/Write 0 W 6 0 5 PCR15 0 W 4 0 3 0 2 PCR12 0 W 1 PCR11 0 W 0 PCR10 0 W 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W 2 PCR12 0 W 1 PCR11 0 W 0 PCR10 0 W In the H8/3854 Group, bits 6, 4, and 3 are reserved, and must always be set to 0. Rev.3.00 Jul. 19, 2007 page 174 of 532 REJ09B0397-0300 8. I/O Ports Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls whether the MOS pull-up of each port 1 pin is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR1 is initialized to H'00. H8/3857 Group Bit 7 6 5 4 3 2 1 0 PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 Initial value Read/Write H8/3854 Group Bit 7 PUCR17 Initial value Read/Write 0 R/W 6 0 5 PUCR15 0 R/W 4 0 3 0 2 1 0 PUCR12 PUCR11 PUCR10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W In the H8/3854 Group, bits 6, 4, and 3 are reserved, and must always be set to 0. Rev.3.00 Jul. 19, 2007 page 175 of 532 REJ09B0397-0300 8. I/O Ports Port Mode Register 1 (PMR1) PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. H8/3857 Group Bit 7 IRQ3 Initial value Read/Write H8/3854 Group Bit 7 IRQ3 Initial value Read/Write 0 R/W 6 0 5 IRQ1 0 R/W 4 0 3 0 2 TMOFH 0 R/W 1 TMOFL 0 R/W 0 TMOW 0 R/W 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 PWM 0 R/W 3 0 2 TMOFH 0 R/W 1 TMOFL 0 R/W 0 TMOW 0 R/W In the H8/3854 Group, bits 6, 4, and 3 are reserved, and must always be set to 0. Bit 7--P17/IRQ3/TMIF Pin Function Switch (IRQ3): This bit selects whether pin P17/IRQ3/TMIF is used as P17 or as IRQ3/TMIF. Bit 7: IRQ3 0 1 Description Functions as P17 I/O pin Functions as IRQ3/TMIF input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ3/TMIF. For details on TMIF pin settings, see Timer Control Register F (TCRF) in section 9.5.2, Register Descriptions. Bit 6--P16/IRQ2/TMIC Pin Function Switch (IRQ2): This bit selects whether pin P16/IRQ2/TMIC is used as P16 or as IRQ2/TMIC. Bit 6: IRQ2 0 1 Description Functions as P16 I/O pin Functions as IRQ2/TMIC input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ2/TMIC. For details on TMIC pin settings, see Timer Mode Register C (TMC) in section 9.4.2, Register Descriptions. Rev.3.00 Jul. 19, 2007 page 176 of 532 REJ09B0397-0300 8. I/O Ports In the H8/3854 Group, bit 6 is reserved, and must always be cleared to 0. Bit 5--P15/IRQ1/TMIB Pin Function Switch (IRQ1): This bit selects whether pin P15/IRQ1/TMIB is used as P15 or as IRQ1/TMIB. Bit 5: IRQ1 0 1 Description Functions as P15 I/O pin Functions as IRQ1/TMIB input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ1/TMIB. For details on TMIB pin settings, see Timer Mode Register B (TMB) in section 9.3.2, Register Descriptions. Bit 4--P14/PWM Pin Function Switch (PWM): This bit selects whether pin P14/PWM is used as P14 or as PWM. Bit 4: PWM 0 1 Description Functions as P14 I/O pin Functions as PWM output pin (initial value) In the H8/3854 Group, bit 4 is reserved, and must always be cleared to 0. Bit 3--Reserved Bit: Bit 3 is reserved; it should always be cleared to 0. Bit 2--P12/TMOFH Pin Function Switch (TMOFH): This bit selects whether pin P12/TMOFH is used as P12 or as TMOFH. Bit 2: TMOFH 0 1 Description Functions as P12 I/O pin Functions as TMOFH output pin (initial value) Bit 1--P11/TMOFL Pin Function Switch (TMOFL): This bit selects whether pin P11/TMOFL is used as P11 or as TMOFL. Bit 1: TMOFL 0 1 Description Functions as P11 I/O pin Functions as TMOFL output pin (initial value) Rev.3.00 Jul. 19, 2007 page 177 of 532 REJ09B0397-0300 8. I/O Ports Bit 0--P10/TMOW Pin Function Switch (TMOW): This bit selects whether pin P10/TMOW is used as P10 or as TMOW. Bit 0: TMOW 0 1 Description Functions as P10 I/O pin Functions as TMOW output pin (initial value) 8.2.3 Pin Functions H8/3857 Group port 1 pin functions are shown in figure 8.3 (a), and H8/3854 Group port 1 pin functions in figure 8.3 (b). Table 8.3 (a) Pin P17/IRQ3/TMIF H8/3857 Group Port 1 Pin Functions Pin Functions and Selection Method The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR17 in PCR1. IRQ3 PCR17 CKSL2 to CKSL0 Pin function 0 *** P17 input pin 0 1 Not 0** P17 output pin IRQ3 input pin 1 * 0** IRQ3/TMIF input pin Note: When using as TMIF input pin, clear bit IEN3 in IENR1 to 0, disabling IRQ3 interrupts. P16/IRQ2/TMIC The pin function depends on bit IRQ2 in PMR1, bits TMC2 to TMC0 in TMC, and bit PCR16 in PCR1. IRQ2 PCR16 TMC2 to TMC0 Pin function 0 *** P16 input pin 0 1 Not 111 P16 output pin IRQ2 input pin 1 * 111 IRQ2/TMIC input pin Note: When using as TMIC input pin, clear bit IEN2 in IENR1 to 0, disabling IRQ2 interrupts. Rev.3.00 Jul. 19, 2007 page 178 of 532 REJ09B0397-0300 8. I/O Ports Pin P15/IRQ1/TMIB Pin Functions and Selection Method The pin function depends on bit IRQ1 in PMR1, bits TMB2 to TMB0 in TMB, and bit PCR15 in PCR1. IRQ1 PCR15 TMB2 to TMB0 Pin function 0 *** P15 input pin 0 1 Not 111 P15 output pin IRQ1 input pin 1 * 111 IRQ1/TMIB input pin Note: When using as TMIB input pin, clear bit IEN1 in IENR1 to 0, disabling IRQ1 interrupts. P14/PWM The pin function depends on bit PWM in PMR1 and bit PCR14 in PCR1. PWM PCR14 Pin function P13 0 P14 input pin 0 1 P14 output pin 1 * PWM output pin The pin function depends on bit PCR13 in PCR1. PCR13 Pin function 0 P13 input pin 1 P13 output pin P12/TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR12 in PCR1. TMOFH PCR12 Pin function 0 P12 input pin 0 1 P12 output pin 1 * TMOFH output pin P11/TMOFL The pin function depends on bit TMOFL in PMR1 and bit PCR11 in PCR1. TMOFL PCR11 Pin function 0 P11 input pin 0 1 P11 output pin 1 * TMOFL output pin P10/TMOW The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1. TMOW PCR10 Pin function 0 P10 input pin 0 1 P10 output pin 1 * TMOW output pin Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 179 of 532 REJ09B0397-0300 8. I/O Ports Table 8.3 (b) Pin P17/IRQ3/TMIF H8/3854 Group Port 1 Pin Functions Pin Functions and Selection Method The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR17 in PCR1. IRQ3 PCR17 CKSL2 to CKSL0 Pin function 0 *** P17 input pin 0 1 Not 0** P17 output pin IRQ3 input pin 1 * 0** IRQ3/TMIF input pin Note: When using as TMIF input pin, clear bit IEN3 in IENR1 to 0, disabling IRQ3 interrupts. P15/IRQ1/TMIB The pin function depends on bit IRQ1 in PMR1, bits TMB2 to TMB0 in TMB, and bit PCR15 in PCR1. IRQ1 PCR15 TMB2 to TMB0 Pin function 0 *** P15 input pin 0 1 Not 111 P15 output pin IRQ1 input pin 1 * 111 IRQ1/TMIB input pin Note: When using as TMIB input pin, clear bit IEN1 in IENR1 to 0, disabling IRQ1 interrupts. P12/TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR12 in PCR1. TMOFH PCR12 Pin function P11/TMOFL 0 P12 input pin 0 1 P12 output pin 1 * TMOFH output pin The pin function depends on bit TMOFL in PMR1 and bit PCR11 in PCR1. TMOFL PCR11 Pin function 0 P11 input pin 0 1 P11 output pin 1 * TMOFL output pin P10/TMOW The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1. TMOW PCR10 Pin function 0 P10 input pin 0 1 P10 output pin 1 * TMOW output pin Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 180 of 532 REJ09B0397-0300 8. I/O Ports 8.2.4 Pin States H8/3857 Group port 1 pin states in each operating mode are shown in table 8.4 (a), and H8/3854 Group port 1 pin states in each operating mode in table 8.4 (b). Table 8.4 (a) Pins P17/IRQ3/TMIF P16/IRQ2/TMIC P15/IRQ1/TMIB P14/PWM P13 P12/TMOFH P11/TMOFL P10/TMOW Note: * A high-level signal is output when the MOS pull-up is in the on state. H8/3857 Group Port 1 Pin States Reset Sleep Subsleep Standby Retains previous state Watch Subactive Active HighRetains impedance previous state HighRetains Functional Functional impedance* previous state Table 8.4 (b) Pins P17/IRQ3/TMIF P15/IRQ1/TMIB P12/TMOFH P11/TMOFL P10/TMOW Note: * H8/3854 Group Port 1 Pin States Reset Sleep Subsleep Standby Retains previous state Watch Subactive Active HighRetains impedance previous state HighRetains Functional Functional impedance* previous state A high-level signal is output when the MOS pull-up is in the on state. Rev.3.00 Jul. 19, 2007 page 181 of 532 REJ09B0397-0300 8. I/O Ports 8.2.5 MOS Input Pull-Up Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset. PCR1n PUCR1n MOS input pull-up 0 Off 0 1 On 1 * Off Legend: * Don't care Notes: H8/3857 Group: n = 7 to 0 H8/3854 Group: n = 7, 5, 2 to 0 8.3 Port 2 Some port 2 functions differ between the H8/3857 Group and the H8/3854 Group. The UD function multiplexed with the P21 pin is provided only in the H8/3857 Group, and not in the H8/3854 Group. POF1 in PMR2 is also a function of the H8/3857 Group only. 8.3.1 Overview Port 2 is an 8-bit I/O port. The H8/3857 Group port 2 pin configuration is shown in figure 8.2 (a), and the H8/3854 Group port 2 pin configuration in figure 8.2 (b). P2 7 P2 6 P2 5 Port 2 P2 4 P2 3 P2 2 P2 1 /UD P2 0 /IRQ 4/ADTRG Figure 8.2 (a) H8/3857 Group Port 2 Pin Configuration Rev.3.00 Jul. 19, 2007 page 182 of 532 REJ09B0397-0300 8. I/O Ports P2 7 P2 6 P2 5 Port 2 P2 4 P2 3 P2 2 P2 1 P2 0 /IRQ 4/ADTRG Figure 8.2 (b) H8/3854 Group Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 2 register configuration. Table 8.5 Name Port data register 2 Port control register 2 Port mode register 2 Port mode register 4 Port 2 Registers Abbr. PDR2 PCR2 PMR2 PMR4 R/W R/W W R/W R/W Initial Value H'00 H'00 H'C0 H'00 Address H'FFD5 H'FFE5 H'FFC9 H'FFCB Port Data Register 2 (PDR2) Bit 7 P27 Initial value Read/Write 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W PDR2 is an 8-bit register that stores data for pins P27 through P20. If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read. Upon reset, PDR2 is initialized to H'00. Rev.3.00 Jul. 19, 2007 page 183 of 532 REJ09B0397-0300 8. I/O Ports Port Control Register 2 (PCR2) Bit 7 PCR27 Initial value Read/Write 0 W 6 PCR26 0 W 5 PCR25 0 W 4 PCR24 0 W 3 PCR23 0 W 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W PCR2 is an 8-bit register for controlling whether each of the port 2 pins P27 to P20 functions as an input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and in PDR2 are valid only when the corresponding pin is designated in PMR2 as a general I/O pin. Upon reset, PCR2 is initialized to H'00. PCR2 is a write-only register. All bits are read as 1. Port Mode Register 2 (PMR2) PMR2 is an 8-bit read/write register, controlling the selection of pin functions for pins P20, P21*, and P43, controlling the PMOS on/off option for pins P32/SO1*. Upon reset, PMR2 is initialized to H'C0. Note: * P21 pin function switching and the P32/SO1 pin are H8/3857 Group functions only, and are not provided in the H8/3854 Group. H8/3857 Group Bit 7 Initial value Read/Write H8/3854 Group Bit 7 Initial value Read/Write 1 6 1 5 0 4 0 3 IRQ0 0 R/W 2 0 1 0 0 IRQ4 0 R/W 1 6 1 5 0 R/W 4 0 R/W 3 IRQ0 0 R/W 2 POF1 0 R/W 1 UD 0 R/W 0 IRQ4 0 R/W In the H8/3854 Group, bits 2 and 1 are reserved, and must always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 184 of 532 REJ09B0397-0300 8. I/O Ports Bits 7 and 6--Reserved Bits: Bits 7 and 6 are reserved; they are always read as 1, and cannot be modified. Bits 5 and 4--Reserved Bits: Bits 5 and 4 are reserved; they should always be cleared to 0. Bit 3--P43/IRQ0 Pin Function Switch (IRQ0): This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0. Bit 3: IRQ0 0 1 Description Functions as P43 input pin Functions as IRQ0 input pin (initial value) Note: Rising or falling edge sensing can be selected for the IRQ0 pin. Bit 2--P32/SO1 Pin PMOS Control (POF1): This bit controls the on/off state of the PMOS transistor in the P32/SO1 pin output buffer. Bit 2: POF1 0 1 Description CMOS output NMOS open-drain output (initial value) In the H8/3854 Group, bit 2 is reserved, and must always be cleared to 0. Bit 1--P21/UD Pin Function Switch (UD): This bit selects whether pin P21/UD is used as P21 or as UD. Bit 1: UD 0 1 Description Functions as P21 I/O pin Functions as UD input pin (initial value) In the H8/3854 Group, bit 1 is reserved, and must always be cleared to 0. Bit 0: P20/IRQ4/ADTRG Pin Function Switch (IRQ4): This bit selects whether pin P20/IRQ4/ADTRG is used as P20 or as IRQ4/ADTRG. Bit 0: IRQ4 0 1 Description Functions as P20 I/O pin Functions as IRQ4/ADTRG input pin (initial value) Note: Rising or falling edge sensing can be selected for the IRQ4 pin. See section 12.3.2, Start of A/D Conversion by External Trigger Input, for the ADTRG pin setting. Rev.3.00 Jul. 19, 2007 page 185 of 532 REJ09B0397-0300 8. I/O Ports Port Mode Register 4 (PMR4) Bit 7 6 5 4 3 2 1 0 NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PMR4 is an 8-bit read/write register, used to select CMOS output or NMOS open drain output for each port 2 pin. Upon reset, PMR4 is initialized to H'00. Bit n--NMOS Open-Drain Output Select (NMODn): This bit selects NMOS open-drain output when pin P2n is used as an output pin. Bit n: NMODn 0 1 Note: n = 7 to 0 Description CMOS output NMOS open-drain output (initial value) Rev.3.00 Jul. 19, 2007 page 186 of 532 REJ09B0397-0300 8. I/O Ports 8.3.3 Pin Functions H8/3857 Group port 2 pin functions are shown in figure 8.6 (a), and H8/3854 Group port 2 pin functions in figure 8.6 (b). Table 8.6 (a) Pin P27 to P22 H8/3857 Group Port 2 Pin Functions Pin Functions and Selection Method Input or output is selected as follows by the bit settings in PCR2. PCR2n Pin function Note: n = 7 to 2 0 P2n input pin 1 P2n output pin P21/UD The pin function depends on bit UD in PMR2 and bit PCR21 in PCR2. UD PCR21 Pin function 0 P21 input pin 0 1 P21 output pin 1 * UD input pin P20/IRQ4/ADTRG The pin function depends on bit IRQ4 in PMR2, bit TRGE in AMR, and bit PCR20 in PCR2. IRQ4 PCR20 TRGE Pin function P20 input pin 0 * 0 1 0 P20 output pin IRQ4 input pin 1 * 1 IRQ4/ADTRG input pin Note: When using as ADTRG input pin, clear bit IEN4 in IENR1 to 0, disabling IRQ4 interrupts. Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 187 of 532 REJ09B0397-0300 8. I/O Ports Table 8.6 (b) Pin P27 to P21 H8/3854 Group Port 2 Pin Functions Pin Functions and Selection Method Input or output is selected as follows by the bit settings in PCR2. PCR2n Pin function Note: n = 7 to 1 0 P2n input pin 1 P2n output pin P20/IRQ4/ADTRG The pin function depends on bit IRQ4 in PMR2, bit TRGE in AMR, and bit PCR20 in PCR2. IRQ4 PCR20 TRGE Pin function P20 input pin 0 * 0 1 0 P20 output pin IRQ4 input pin 1 * 1 IRQ4/ADTRG input pin Note: When using as ADTRG input pin, clear bit IEN4 in IENR1 to 0, disabling IRQ4 interrupts. Legend: * Don't care 8.3.4 Pin States H8/3857 Group port 2 pin states in each operating mode are shown in table 8.7 (a), and H8/3854 Group port 2 pin states in each operating mode in table 8.7 (b). Table 8.7 (a) Pins P27 to P22 P21/UD P20/IRQ4/ ADTRG H8/3857 Group Port 2 Pin States Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Retains Functional Functional previous state Table 8.7 (b) Pins P27 to P21 P20/IRQ4/ ADTRG H8/3854 Group Port 2 Pin States Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Retains Functional Functional previous state Rev.3.00 Jul. 19, 2007 page 188 of 532 REJ09B0397-0300 8. I/O Ports 8.4 Port 3 (H8/3857 Group Only) Port 3 is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. 8.4.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8.3. P3 7 P3 6 P3 5 Port 3 P3 4 P3 3 P3 2 /SO 1 P3 1 /SI1 P3 0 /SCK1 Figure 8.3 Port 3 Pin Configuration 8.4.2 Register Configuration and Description Table 8.8 shows the port 3 register configuration. Table 8.8 Name Port data register 3 Port control register 3 Port pull-up control register 3 Port mode register 3 Port 3 Registers Abbr. PDR3 PCR3 PUCR3 PMR3 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD6 H'FFE6 H'FFE1 H'FFCA Rev.3.00 Jul. 19, 2007 page 189 of 532 REJ09B0397-0300 8. I/O Ports Port Data Register 3 (PDR3) Bit 7 P37 Initial value Read/Write 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P30 0 R/W PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read. Upon reset, PDR3 is initialized to H'00. Port Control Register 3 (PCR3) Bit 7 PCR37 Initial value Read/Write 0 W 6 PCR36 0 W 5 PCR35 0 W 4 PCR34 0 W 3 PCR33 0 W 2 PCR32 0 W 1 PCR31 0 W 0 PCR30 0 W PCR3 is an 8-bit register for controlling whether each of the port 3 pins P37 to P30 functions as an input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I/O pin. Upon reset, PCR3 is initialized to H'00. PCR3 is a write-only register. All bits are read as 1. Port Pull-Up Control Register 3 (PUCR3) Bit 7 6 5 4 3 2 1 0 PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PUCR3 bits control the on/off state of pin P37-P30 MOS pull-ups. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Rev.3.00 Jul. 19, 2007 page 190 of 532 REJ09B0397-0300 8. I/O Ports Upon reset, PUCR3 is initialized to H'00. Port Mode Register 3 (PMR3) Bit 7 Initial value Read/Write 0 6 0 5 0 4 0 3 0 2 SO1 0 R/W 1 SI1 0 R/W 0 SCK1 0 R/W PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'00. Bits 7 to 3--Reserved Bits: Bits 7 to 3 are reserved; they should always be cleared to 0. Bit 2--P32/SO1 Pin Function Switch (SO1): This bit selects whether pin P32/SO1 is used as P32 or as SO1. Bit 2: SO1 0 1 Description Functions as P32 I/O pin Functions as SO1 output pin (initial value) Bit 1--P31/SI1 Pin Function Switch (SI1): This bit selects whether pin P31/SI1 is used as P31 or as SI1. Bit 1: SI1 0 1 Description Functions as P31 I/O pin Functions as SI1 input pin (initial value) Bit 0--P30/SCK1 Pin Function Switch (SCK1): This bit selects whether pin P30/SCK1 is used as P30 or as SCK1. Bit 0: SCK1 0 1 Description Functions as P30 I/O pin Functions as SCK1 I/O pin (initial value) Rev.3.00 Jul. 19, 2007 page 191 of 532 REJ09B0397-0300 8. I/O Ports 8.4.3 Pin Functions Table 8.9 shows the port 3 pin functions. Table 8.9 Pin P37 to P33 Port 3 Pin Functions Pin Functions and Selection Method The pin function depends on the corresponding bit in PCR3. PCR3n Pin function Note: n = 7 to 3 0 P3n input pin 1 P3n output pin P32/SO1 The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3. SO1 PCR32 Pin function 0 P32 input pin 0 1 P32 output pin 1 * SO1 output pin P31/SI1 The pin function depends on bit SI1 in PMR3 and bit PCR31 in PCR3. SI1 PCR31 Pin function 0 P31 input pin 0 1 P31 output pin 1 * SI1 input pin P30/SCK1 The pin function depends on bit SCK1 in PMR3, bit CKS3 in SCR1, and bit PCR30 in PCR3. SCK1 CKS3 PCR30 Pin function 0 P30 input pin 0 * 1 P30 output pin 0 * SCK1 output pin 1 1 * SCK1 input pin Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 192 of 532 REJ09B0397-0300 8. I/O Ports 8.4.4 Pin States Table 8.10 shows the port 3 pin states in each operating mode. Table 8.10 Port 3 Pin States Pins P37 to P33 P32/SO1 P31/SI1 P30/SCK1 Note: * A high-level signal is output when the MOS pull-up is in the on state. Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Watch Subactive Active HighRetains Functional Functional impedance* previous state 8.4.5 MOS Input Pull-Up Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR3n PUCR3n MOS input pull-up Legend: * Don't care Note: n = 7 to 0 0 Off 0 1 On 1 * Off Rev.3.00 Jul. 19, 2007 page 193 of 532 REJ09B0397-0300 8. I/O Ports 8.5 Port 4 Port 4 functions are common to the H8/3857 Group and H8/3854 Group. 8.5.1 Overview Port 4 consists of a 3-bit I/O port and a 1-bit input port, and is configured as shown in figure 8.4. P4 3 /IRQ 0 Port 4 P4 2 /TXD P4 1 /RXD P4 0 /SCK 3 Figure 8.4 Port 4 Pin Configuration 8.5.2 Register Configuration and Description Table 8.11 shows the port 4 register configuration. Table 8.11 Port 4 Registers Name Port data register 4 Port control register 4 Abbr. PDR4 PCR4 R/W R/W W Initial Value H'F8 H'F8 Address H'FFD7 H'FFE7 Rev.3.00 Jul. 19, 2007 page 194 of 532 REJ09B0397-0300 8. I/O Ports Port Data Register 4 (PDR4) Bit 7 Initial value Read/Write 1 6 1 5 1 4 1 3 P43 Undefined 2 P42 0 R/W 1 P41 0 R/W 0 P40 0 R/W R PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is read while PCR4 bits are cleared to 0, the pin states are read. The pin state is always read from bit 3 (P43). Upon reset, PDR4 is initialized to H'F8. Port Control Register 4 (PCR4) Bit 7 Initial value Read/Write 1 6 1 5 1 4 1 3 1 2 PCR42 0 W 1 PCR41 0 W 0 PCR40 0 W PCR4 controls whether each of the port 4 pins P42 to P40 functions as an input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR4 and in PDR4 are valid only when the corresponding pin is designated in SCR3 as a general I/O pin. Upon reset, PCR4 is initialized to H'F8. PCR4 is a write-only register. All bits are read as 1. Rev.3.00 Jul. 19, 2007 page 195 of 532 REJ09B0397-0300 8. I/O Ports 8.5.3 Pin Functions Table 8.12 shows the port 4 pin functions. Table 8.12 Port 4 Pin Functions Pin P43/IRQ0 Pin Functions and Selection Method The pin function depends on the IRQ0 bit setting in PMR2. IRQ0 Pin function P42/TXD 0 P43 input pin 1 IRQ0 input pin The pin function depends on bit TE in SCR3 and bit PCR42 in PCR4. TE PCR42 Pin function 0 P42 input pin 0 1 P42 output pin 1 * TXD output pin P41/RXD The pin function depends on bit RE in SCR3 and bit PCR41 in PCR4. RE PCR41 Pin function 0 P41 input pin 0 1 P41 output pin 1 * RXD input pin P40/SCK3 The pin function depends on bits CKE1 and CKE0 in SCR3, bit COM in SMR, and bit PCR40 in PCR4. CKE1 CKE0 COM PCR40 Pin function 0 P40 input pin 0 1 P40 output pin 0 1 * SCK3 output pin 0 1 * 1 * * * SCK3 input pin Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 196 of 532 REJ09B0397-0300 8. I/O Ports 8.5.4 Pin States Table 8.13 shows the port 4 pin states in each operating mode. Table 8.13 Port 4 Pin States Pins P43/IRQ0 P42/TXD P41/RXD P40/SCK3 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Retains Functional Functional previous state 8.6 Port 5 Port 5 functions are common to the H8/3857 Group and H8/3854 Group. 8.6.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8.5. P5 7 /WKP7 P5 6 /WKP6 P5 5 /WKP5 Port 5 P5 4 /WKP4 P5 3 /WKP3 P5 2 /WKP2 P5 1 /WKP1 P5 0 /WKP0 Figure 8.5 Port 5 Pin Configuration Rev.3.00 Jul. 19, 2007 page 197 of 532 REJ09B0397-0300 8. I/O Ports 8.6.2 Register Configuration and Description Table 8.14 shows the port 5 register configuration. Table 8.14 Port 5 Registers Name Port data register 5 Port control register 5 Port pull-up control register 5 Port mode register 5 Abbr. PDR5 PCR5 PUCR5 PMR5 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD8 H'FFE8 H'FFE2 H'FFCC Port Data Register 5 (PDR5) Bit 7 P57 Initial value Read/Write 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read. Upon reset, PDR5 is initialized to H'00. Port Control Register 5 (PCR5) Bit 7 PCR57 Initial value Read/Write 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W 2 PCR52 0 W 1 PCR51 0 W 0 PCR50 0 W PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR5 is initialized to H'00. PCR5 is a write-only register. All bits are read as 1. Rev.3.00 Jul. 19, 2007 page 198 of 532 REJ09B0397-0300 8. I/O Ports Port Pull-up Control Register 5 (PUCR5) Bit 7 6 5 4 3 2 1 0 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PUCR5 bits control the on/off state of pin P57-P50 MOS pull-ups. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR5 is initialized to H'00. Port Mode Register 5 (PMR5) Bit 7 WKP7 Initial value Read/Write 0 R/W 6 WKP6 0 R/W 5 WKP5 0 R/W 4 WKP4 0 R/W 3 WKP3 0 R/W 2 WKP2 0 R/W 1 WKP1 0 R/W 0 WKP0 0 R/W PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n--P5n/WKPn Pin Function Switch (WKPn): This bit selects whether pin P5n/WKPn is used as P5n or as WKPn. Bit n: WKPn 0 1 Note: n = 7 to 0 Description Functions as P5n I/O pin Functions as WKPn input pin (initial value) Rev.3.00 Jul. 19, 2007 page 199 of 532 REJ09B0397-0300 8. I/O Ports 8.6.3 Pin Functions Table 8.15 shows the port 5 pin functions. Table 8.15 Port 5 Pin Functions Pin P57/WKP7 to P50/WKP0 Pin Functions and Selection Method The pin function depends on bit WKPn in PMR5 and bit PCR5n in PCR5. WKPn PCR5n Pin function 0 P5n input pin 0 1 P5n output pin 1 * WKPn input pin Legend: * Don't care Note: n = 7 to 0 8.6.4 Pin States Table 8.16 shows the port 5 pin states in each operating mode. Table 8.16 Port 5 Pin States Pins P57/WKP7 to P50/WKP0 Note: * Reset Sleep Subsleep Retains previous state Standby Watch Subactive Active HighRetains impedance previous state HighRetains Functional Functional impedance* previous state A high-level signal is output when the MOS pull-up is in the on state. 8.6.5 MOS Input Pull-Up Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR5n PUCR5n MOS input pull-up Legend: * Don't care Note: n = 7 to 0 Rev.3.00 Jul. 19, 2007 page 200 of 532 REJ09B0397-0300 0 Off 0 1 On 1 * Off 8. I/O Ports 8.7 Port 9 [Chip-Internal I/O port] Port 9 functions are common to the H8/3857 Group and H8/3854 Group. 8.7.1 Overview Port 9 is an 8-bit I/O port that interfaces to the on-chip LCD controller. The port 9 pin configuration is shown in figure 8.6. P97 P96 P95 Port 9 P94 P93 P92 P91 P90 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LCD controller Note: Dotted lines indicate connections inside the chip. Figure 8.6 Port 9 Pin Configuration 8.7.2 Register Configuration and Description Table 8.17 shows the port 9 register configuration. Table 8.17 Port 9 Registers Name Port data register 9 Port control register 9 Abbr. PDR9 PCR9 R/W R/W W Initial Value H'00 H'00 Address H'FFDC H'FFEC Rev.3.00 Jul. 19, 2007 page 201 of 532 REJ09B0397-0300 8. I/O Ports Port Data Register 9 (PDR9) Bit 7 P97 Initial value Read/Write 0 R/W 6 P96 0 R/W 5 P95 0 R/W 4 P94 0 R/W 3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W 0 P90 0 R/W PDR9 is an 8-bit register that stores data for port 9 pins P97 to P90. If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read. Upon reset, PDR9 is initialized to H'00. Port Control Register 9 (PCR9) Bit 7 PCR97 Initial value Read/Write 0 W 6 PCR96 0 W 5 PCR95 0 W 4 PCR94 0 W 3 PCR93 0 W 2 PCR92 0 W 1 PCR91 0 W 0 PCR90 0 W PCR9 is an 8-bit register for controlling whether each of the port 9 pins P97 to P90 functions as an input or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR9 is initialized to H'00. PCR9 is a write-only register. All bits are read as 1. 8.7.3 Pin Functions Table 8.18 shows the port 9 pin functions. Table 8.18 Port 9 Pin Functions Pin P97 to P90 Pin Functions and Selection Method The pin function depends on the corresponding bit in PCR9. PCR9n Pin function Note: n = 7 to 0 0 P9n input pin 1 P9n output pin Rev.3.00 Jul. 19, 2007 page 202 of 532 REJ09B0397-0300 8. I/O Ports 8.7.4 Pin States Table 8.19 shows the port 9 pin states in each operating mode. Table 8.19 Port 9 Pin States Pins P97 to P90 Reset Sleep Subsleep Standby Retains previous state Highimpedance Watch Subactive Active HighRetains impedance previous state Retains Functional Functional previous state 8.8 Port A [Chip-Internal I/O port] Port A functions are common to the H8/3857 Group and H8/3854 Group. 8.8.1 Overview Port A is a 4-bit I/O port that interfaces to the on-chip LCD controller. The port A pin configuration is shown in figure 8.7. PA3 Port A PA2 PA1 PA0 RS R/W STRB LCD controller Note: Dotted lines indicate connections inside the chip. Figure 8.7 Port A Pin Configuration Rev.3.00 Jul. 19, 2007 page 203 of 532 REJ09B0397-0300 8. I/O Ports 8.8.2 Register Configuration and Description Table 8.20 shows the port A register configuration. Table 8.20 Port A Registers Name Port data register A Port control register A Abbr. PDRA PCRA R/W R/W W Initial Value H'F0 H'F0 Address H'FFDD H'FFED Port Data Register A (PDRA) Bit 7 Initial value Read/Write 1 6 1 5 1 4 1 3 PA3 0 R/W 2 PA2 0 R/W 1 PA1 0 R/W 0 PA0 0 R/W PDRA is an 8-bit register that stores data for port A pins PA3 to PA0. If port A is read while PCRA bits are set to 1, the values stored in PDRA are read. If port A is read while PCRA bits are cleared to 0, the pin states are read. Upon reset, PDRA is initialized to H'F0. Port Control Register A (PCRA) Bit 7 Initial value Read/Write 1 6 1 5 1 4 1 3 PCRA3 0 W 2 PCRA2 0 W 1 PCRA1 0 W 0 PCRA0 0 W PCRA is an 8-bit register for controlling whether each of the port A pins PA3 to PA0 functions as an input or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCRA is initialized to H'F0. PCRA is a write-only register. All bits are read as 1. Rev.3.00 Jul. 19, 2007 page 204 of 532 REJ09B0397-0300 8. I/O Ports 8.8.3 Pin Functions Table 8.21 gives the port A pin functions. Table 8.21 Port A Pin Functions Pin PA3 to PA0 Pin Functions and Selection Method The pin function depends on the corresponding bit in PCRA. PCRAn Pin function Note: n = 3 to 0 0 PAn input pin 1 PAn output pin 8.8.4 Pin States Table 8.22 shows the port A pin states in each operating mode. Table 8.22 Port A Pin States Pins PA3 to PA0 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Retains Functional Functional previous state Rev.3.00 Jul. 19, 2007 page 205 of 532 REJ09B0397-0300 8. I/O Ports 8.9 Port B Some port B functions differ between the H8/3857 Group and the H8/3854 Group. Pins PB3 to PB0/AN3 to AN0 are provided only in the H8/3857 Group, and not in the H8/3854 Group. 8.9.1 Overview Port B is an 8-bit input-only port. The H8/3857 Group port B pin configuration is shown in figure 8.8 (a), and the H8/3854 Group port B pin configuration in figure 8.8 (b). PB7 /AN 7 PB6 /AN 6 PB5 /AN 5 Port B PB4 /AN 4 PB3 /AN 3 PB2 /AN 2 PB1 /AN 1 PB0 /AN 0 Figure 8.8 (a) H8/3857 Group Port B Pin Configuration PB7/AN7 Port B PB6/AN6 PB5/AN5 PB4/AN4 Figure 8.8 (b) H8/3854 Group Port B Pin Configuration Rev.3.00 Jul. 19, 2007 page 206 of 532 REJ09B0397-0300 8. I/O Ports 8.9.2 Register Configuration and Description Table 8.23 shows the port B register configuration. Table 8.23 Port B Register Name Port data register B Abbr. PDRB R/W R Address H'FFDE Port Data Register B (PDRB) Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage. H8/3857 Group Bit 7 PB7 Read/Write H8/3854 Group Bit 7 PB7 Read/Write R 6 PB6 R 5 PB5 R 4 PB4 R 3 2 1 0 R 6 PB6 R 5 PB5 R 4 PB4 R 3 PB3 R 2 PB2 R 1 PB1 R 0 PB0 R In the H8/3854 Group, bits 3 to 0 are reserved. Rev.3.00 Jul. 19, 2007 page 207 of 532 REJ09B0397-0300 8. I/O Ports Rev.3.00 Jul. 19, 2007 page 208 of 532 REJ09B0397-0300 9. Timers Section 9 Timers 9.1 Overview The H8/3857 Group is provided with four timers (timers A, B, C, and F), and the H8/3854 Group with three (timers A, B, and F). The H8/3857F and H8/3854F also have an on-chip watchdog timer for flash memory programming control. Table 9.1 outlines the functions of timers A, B, C, F, and the watchdog timer. Table 9.1 Name Timer A Timer Functions Functions * * * * 8-bit timer Interval timer 8-bit timer Time base Internal Clock /8 to /8192 (8 choices) Event Input Pin Waveform Output Pin Remarks W/128 (choice of 4 overflow periods) /4 to /32, W/4 to W/32 (8 choices) /4 to /8192 (7 choices) /4 to /8192, W/4 (7 choices) * 8-bit timer * Clock output * * * 1 Timer C* * * * * Timer B Timer F * * * 8-bit timer Interval timer Event counter 8-bit timer Interval timer Event counter Choice of up- or downcounting 16-bit timer Event counter Can be used as two independent 8-bit timers Output compare Generates reset signal on overflow of 8-bit counter TMOW TMIB TMIC Counting direction can be controlled by software or hardware /2 to /32 (4 choices) TMIF TMOFL TMOFH * Watchdog * timer*2 /64 to /8192 (8 choices) Provided only in H8/3857F and H8/3854F Notes: 1. Timer C is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. 2. The watchdog timer is used by the flash memory programming control program. Rev.3.00 Jul. 19, 2007 page 209 of 532 REJ09B0397-0300 9. Timers 9.2 9.2.1 Timer A Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. Features Features of timer A are given below. * Choice of eight internal clock sources (/8192, /4096, /2048, /512, /256, /128, /32, /8). * Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock time base (using a 32.768 kHz crystal oscillator). * An interrupt is requested when the counter overflows. * Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8, or 4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32, 16, 8, or 4. Rev.3.00 Jul. 19, 2007 page 210 of 532 REJ09B0397-0300 9. Timers Block Diagram Figure 9.1 shows a block diagram of timer A. W 1/4 W/4 W/32 W/16 W/8 W/4 PSW TMA W/128 TCA /8192, /4096, /2048, /512, /256, /128, /32, /8 PSS /8* /64* /128* /256* TMOW W/32 W/16 W/8 W/4 IRRTA Legend: TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS: Prescaler S Note: * Can be selected only when the prescaler W output (W/128) is used as the TCA input clock. Figure 9.1 Block Diagram of Timer A Pin Configuration Table 9.2 shows the timer A pin configuration. Table 9.2 Name Clock output Pin Configuration Abbr. TMOW I/O Output Function Output of waveform generated by timer A output circuit Rev.3.00 Jul. 19, 2007 page 211 of 532 REJ09B0397-0300 Internal data bus 9. Timers Register Configuration Table 9.3 shows the register configuration of timer A. Table 9.3 Name Timer mode register A Timer counter A Timer A Registers Abbr. TMA TCA R/W R/W R Initial Value H'10 H'00 Address H'FFB0 H'FFB1 9.2.2 Register Descriptions Timer Mode Register A (TMA) Bit 7 TMA7 Initial value Read/Write 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 1 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. Upon reset, TMA is initialized to H'10. Bits 7 to 5--Clock Output Select (TMA7 to TMA5): Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. Bit 7: TMA7 0 Bit 6: TMA6 0 Bit 5: TMA5 0 1 1 0 1 1 0 0 1 1 0 1 Clock Output /32 /16 /8 /4 W/32 W/16 W/8 W/4 (initial value) Rev.3.00 Jul. 19, 2007 page 212 of 532 REJ09B0397-0300 9. Timers Bit 4--Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0--Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA. Description Bit 3: TMA3 0 Bit 2: TMA2 0 Bit 1: TMA1 0 Bit 0: TMA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Prescaler and Divider Ratio or Overflow Period PSS, /8192 PSS, /4096 PSS, /2048 PSS, /512 PSS, /256 PSS, /128 PSS, /32 PSS, /8 PSW, 1 s PSW, 0.5 s PSW, 0.25 s PSW, 0.03125 s PSW and TCA are reset Clock time base (initial value) Function Interval timer Timer Counter A (TCA) Bit 7 TCA7 Initial value Read/Write 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R 0 TCA0 0 R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11. Rev.3.00 Jul. 19, 2007 page 213 of 532 REJ09B0397-0300 9. Timers Upon reset, TCA is initialized to H'00. 9.2.3 Timer Operation Interval Timer Operation: When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested.* At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. Note: * For details on interrupts, see section 3.3, Interrupts. Real-Time Clock Time Base Operation: When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00. Clock Output: Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. Rev.3.00 Jul. 19, 2007 page 214 of 532 REJ09B0397-0300 9. Timers 9.2.4 Timer A Operation States Table 9.4 summarizes the timer A operation states. Table 9.4 Timer A Operation States Reset Active Reset Reset Reset Sleep Watch Subactive Halted Subsleep Halted Standby Halted Retained Operation Mode TCA Interval Clock time base TMA Functions Functions Halted Functions Retained Retained Functions Functions Functions Functions Functions Halted Functions Retained Note: When real-time clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/ (s) in the count cycle. 9.3 9.3.1 Timer B Overview Timer B is an 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. Features Features of timer B are given below. * Choice of seven internal clock sources (/8192, /2048, /512, /256, /64, /16, /4) or an external clock (can be used to count external events). * An interrupt is requested when the counter overflows. Block Diagram Figure 9.2 shows a block diagram of timer B. Rev.3.00 Jul. 19, 2007 page 215 of 532 REJ09B0397-0300 9. Timers TMB PSS TCB TMIB TLB Legend: TMB: Timer mode register B Timer counter B TCB: Timer load register B TLB: IRRTB: Timer B overflow interrupt request flag Prescaler S PSS: Figure 9.2 Block Diagram of Timer B Pin Configuration Table 9.5 shows the timer B pin configuration. Table 9.5 Name Timer B event input Pin Configuration Abbr. TMIB I/O Input Function Event input to TCB Register Configuration Table 9.6 shows the register configuration of timer B. Table 9.6 Name Timer mode register B Timer counter B Timer load register B Timer B Registers Abbr. TMB TCB TLB R/W R/W R W Initial Value H'78 H'00 H'00 Address H'FFB2 H'FFB3 H'FFB3 Rev.3.00 Jul. 19, 2007 page 216 of 532 REJ09B0397-0300 Internal data bus IRRTB 9. Timers 9.3.2 Register Descriptions Timer Mode Register B (TMB) Bit 7 TMB7 Initial value Read/Write 0 R/W 6 1 5 1 4 1 3 1 2 TMB2 0 R/W 1 TMB1 0 R/W 0 TMB0 0 R/W TMB is an 8-bit read/write register for selecting the auto-reload function and input clock. Upon reset, TMB is initialized to H'78. Bit 7--Auto-Reload Function Select (TMB7): Bit 7 selects whether timer B is used as an interval timer or auto-reload timer. Bit 7: TMB7 0 1 Description Interval timer function selected Auto-reload function selected (initial value) Bits 6 to 3--Reserved Bits: Bits 6 to 3 are reserved; they always read 1, and cannot be modified. Bits 2 to 0--Clock Select (TMB2 to TMB0): Bits 2 to 0 select the clock input to TCB. For external event counting, either the rising or falling edge can be selected. Bit 2: TMB2 0 Bit 1: TMB1 0 Bit 0: TMB0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description Internal clock: /8192 Internal clock: /2048 Internal clock: /512 Internal clock: /256 Internal clock: /64 Internal clock: /16 Internal clock: /4 External event (TMIB): rising or falling edge* (initial value) The edge of the external event signal is selected by bit IEG1 in the IRQ edge select register (IEGR). See section 3.3.2, Interrupt Control Registers, for details on the IRQ edge select register. Be sure to set bit IRQ1 in port mode register 1 (PMR1) to 1 before setting bits TMB2 to TMB0 to 111. Rev.3.00 Jul. 19, 2007 page 217 of 532 REJ09B0397-0300 9. Timers Timer Counter B (TCB) Bit 7 TCB7 Initial value Read/Write 0 R 6 TCB6 0 R 5 TCB5 0 R 4 TCB4 0 R 3 TCB3 0 R 2 TCB2 0 R 1 TCB1 0 R 0 TCB0 0 R TCB is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode register B (TMB). TCB values can be read by the CPU at any time. When TCB overflows from H'FF to H'00 or to the value set in TLB, the IRRTB bit in interrupt request register 2 (IRR2) is set to 1. TCB is allocated to the same address as timer load register B (TLB). Upon reset, TCB is initialized to H'00. Timer Load Register B (TLB) Bit 7 TLB7 Initial value Read/Write 0 W 6 TLB6 0 W 5 TLB5 0 W 4 TLB4 0 W 3 TLB3 0 W 2 TLB2 0 W 1 TLB1 0 W 0 TLB0 0 W TLB is an 8-bit write-only register for setting the reload value of timer counter B. When a reload value is set in TLB, the same value is loaded into timer counter B (TCB) as well, and TCB starts counting up from that value. When TCB overflows during operation in auto-reload mode, the TLB value is loaded into TCB. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLB as to TCB. Upon reset, TLB is initialized to H'00. Rev.3.00 Jul. 19, 2007 page 218 of 532 REJ09B0397-0300 9. Timers 9.3.3 Timer Operation Interval timer Operation: When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer B functions as an 8-bit interval timer. Upon reset, TCB is cleared to H'00 and bit TMB7 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer B is selected from seven internal clock signals output by prescaler S, or an external clock input at pin TMIB. The selection is made by bits TMB2 to TMB0 of TMB. After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow, setting bit IRRTB to 1 in interrupt request register 2 (IRR2). If IENTB = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow, TCB returns to H'00 and starts counting up again. During interval timer operation (TMB7 = 0), when a value is set in timer load register B (TLB), the same value is set in TCB. Note: * For details on interrupts, see section 3.3, Interrupts. Auto-Reload Timer Operation: Setting bit TMB7 in TMB to 1 causes timer B to function as an 8-bit auto-reload timer. When a reload value is set in TLB, the same value is loaded into TCB, becoming the value from which TCB starts its count. After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow. The TLB value is then loaded into TCB, and the count continues from that value. The overflow period can be set within a range from 1 to 256 input clocks, depending on the TLB value. The clock sources and interrupts in auto-reload mode are the same as in interval mode. In auto-reload mode (TMB7 = 1), when a new value is set in TLB, the TLB value is also set in TCB. Event Counter Operation: Timer B can operate as an event counter, counting rising or falling edges of an external event signal input at pin TMIB. External event counting is selected by setting bits TMB2 to TMB0 in timer mode register B to all 1s (111). When timer B is used to count external event input, bit IRQ1 in port mode register 1 (PMR1) should be set to 1, and bit IEN1 in interrupt enable register 1 (IENR1) should be cleared to 0 to disable IRQ1 interrupt requests. Rev.3.00 Jul. 19, 2007 page 219 of 532 REJ09B0397-0300 9. Timers 9.3.4 Timer B Operation States Table 9.7 summarizes the timer B operation states. Table 9.7 Timer B Operation States Reset Reset Reset Reset Active Functions Functions Functions Sleep Functions Functions Retained Watch Halted Halted Retained Subactive Halted Halted Retained Subsleep Halted Halted Retained Standby Halted Halted Retained Operation Mode TCB Interval Auto reload TMB 9.4 9.4.1 Timer C (H8/3857 Group Only) Overview Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This timer has two operation modes, interval and auto reload. Timer C is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. Features The main features of timer C are given below. * Choice of seven internal clock sources (/8192, /2048, /512, /64, /16, /4, W/4) or an external clock (can be used to count external events). * An interrupt is requested when the counter overflows. * Can be switched between up- and down-counting by software or hardware. * When W/4 is selected as the internal clock source, or when an external clock is selected, timer C can function in subactive mode and subsleep mode. Rev.3.00 Jul. 19, 2007 page 220 of 532 REJ09B0397-0300 9. Timers Block Diagram Figure 9.3 shows a block diagram of timer C. TMC UD TMIC W/4 TLC PSS TCC Legend: TMC: Timer mode register C TCC: Timer counter C Timer load register C TLC: IRRTC: Timer C overflow interrupt request flag PSS: Prescaler S IRRTC Figure 9.3 Block Diagram of Timer C Pin Configuration Table 9.8 shows the timer C pin configuration. Table 9.8 Name Timer C event input Timer C up/down control Pin Configuration Abbr. TMIC UD I/O Input Input Function Event input to TCC Selection of counting direction Register Configuration Table 9.9 shows the register configuration of timer C. Rev.3.00 Jul. 19, 2007 page 221 of 532 REJ09B0397-0300 Internal data bus 9. Timers Table 9.9 Name Timer C Registers Abbr. TMC TCC TLC R/W R/W R W Initial Value H'18 H'00 H'00 Address H'FFB4 H'FFB5 H'FFB5 Timer mode register C Timer counter C Timer load register C 9.4.2 Register Descriptions Timer Mode Register C (TMC) Bit 7 TMC7 Initial value Read/Write 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 1 3 1 2 TMC2 0 R/W 1 TMC1 0 R/W 0 TMC0 0 R/W TMC is an 8-bit read/write register for selecting the auto-reload function, counting direction, and input clock. Upon reset, TMC is initialized to H'18. Bit 7--Auto-Reload Function Select (TMC7): Bit 7 selects whether timer C is used as an interval timer or auto-reload timer. Bit 7: TMC7 0 1 Description Interval timer function selected Auto-reload function selected (initial value) Bits 6 and 5--Counter Up/Down Control (TMC6, TMC5): These bits select the counting direction of timer counter C (TCC), or allow hardware to control the counting direction using pin UD. Bit 6: TMC6 0 Bit 5: TMC5 0 1 1 * Description TCC is an up-counter TCC is a down-counter TCC up/down control is determined by input at pin UD. TCC is a down-counter if the UD input is high, and an upcounter if the UD input is low. (initial value) Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 222 of 532 REJ09B0397-0300 9. Timers Bits 4 and 3--Reserved Bits: Bits 4 and 3 are reserved; they are always read as 1, and cannot be modified. Bits 2 to 0--Clock Select (TMC2 to TMC0): Bits 2 to 0 select the clock input to TCC. For external clock counting, either the rising or falling edge can be selected. Bit 2: TMC2 0 Bit 1: TMC1 0 Bit 0: TMC0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description Internal clock: /8192 Internal clock: /2048 Internal clock: /512 Internal clock: /64 Internal clock: /16 Internal clock: /4 Internal clock: W/4 External event (TMIC): rising or falling edge* (initial value) The edge of the external event signal is selected by bit IEG2 in the IRQ edge select register (IEGR). See section 3.3.2, Interrupt Control Registers for details on the IRQ edge select register. Be sure to set bit IRQ2 in port mode register 1 (PMR1) to 1 before setting bits TMC2 to TMC0 to 111. Timer Counter C (TCC) Bit Initial value Read/Write 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R 2 TCC2 0 R 1 TCC1 0 R 0 TCC0 0 R TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time. When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1. TCC is allocated to the same address as timer load register C (TLC). Upon reset, TCC is initialized to H'00. Rev.3.00 Jul. 19, 2007 page 223 of 532 REJ09B0397-0300 9. Timers Timer Load Register C (TLC) Bit 7 TLC7 Initial value Read/Write 0 W 6 TLC6 0 W 5 TLC5 0 W 4 TLC4 0 W 3 TLC3 0 W 2 TLC2 0 W 1 TLC1 0 W 0 TLC0 0 W TLC is an 8-bit write-only register for setting the reload value of TCC. When a reload value is set in TLC, the same value is loaded into timer counter C (TCC) as well, and TCC starts counting up or down from that value. When TCC overflows or underflows during operation in auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow and underflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLC as to TCC. Upon reset, TLC is initialized to H'00. 9.4.3 Timer Operation Interval Timer Operation: When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit interval timer. Upon reset, timer counter C (TCC) is initialized to H'00 and TMC to H'18. After a reset, the counter continues uninterrupted incrementing as an interval up-counter. The clock input to timer C is selected from seven internal clock signals output by prescalers S and W, or an external clock input at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC. Either software or hardware can control whether TCC counts up or down. The selection is made by TMC bits TMC6 and TMC5. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (underflow), setting bit IRRTC to 1 in interrupt request register 2 (IRR2). If IENTC = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow or underflow, TCC returns to H'00 or H'FF and starts counting up or down again. During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: * For details on interrupts, see section 3.3, Interrupts. Rev.3.00 Jul. 19, 2007 page 224 of 532 REJ09B0397-0300 9. Timers Auto-Reload Timer Operation: Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (underflow). The TLC value is then loaded TCC, and the count continues from that value. The overflow (underflow) period can be set within a range from 1 to 256 input clocks, depending on the TLC value. The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in TCC. Event Counter Operation: Timer C can operate as an event counter, counting an event signal input at pin TMIC. External event counting is selected by setting TMC bits TMC2 to TMC0 to all 1s (111). TCC counts up or down at the rising or falling edge of the input at pin TMIC. When timer C is used to count external event inputs, bit IRQ2 in port mode register 1 (PMR1) should be set to 1, and bit IEN2 in interrupt enable register 1 (IENR1) should be cleared to 0 to disable IRQ2 interrupt requests. TCC Up/Down Control by Hardware: The counting direction of timer C can be controlled by input at pin UD. When bit TMC6 in TMC is set to 1, high-level input at the UD pin selects downcounting, while low-level input selects up-counting. When using input at pin UD for this control function, set the UD bit in port mode register 2 (PMR2) to 1. Rev.3.00 Jul. 19, 2007 page 225 of 532 REJ09B0397-0300 9. Timers 9.4.4 Timer C Operation States Table 9.10 summarizes the timer C operation states. Table 9.10 Timer C Operation States Operation Mode TCC TCC TMC Note: * Interval Auto reload Reset Active Reset Functions Reset Functions Reset Functions Sleep Functions Functions Retained Watch Halted Halted Retained Subactive Functions/ Halted* Functions/ Halted* Functions Subsleep Standby Functions/ Halted Halted* Functions/ Halted Halted* Retained Retained When W/4 is selected as the internal clock of TCC in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/ (s) in the count cycle. When timer C is operated in subactive mode or subsleep mode, either an external clock or the W/4 internal clock must be selected. The counter will not operate in these modes if another clock is selected. If the internal W/4 clock is selected when W/8 is being used as the subclock SUB, the lower 2 bits of the counter will operate on the same cycle, with the least significant bit not being counted. 9.5 9.5.1 Timer F Overview Timer F is a 16-bit timer with an output compare function. Compare match signals can be used to reset the counter, request an interrupt, or toggle the output. Timer F can also be used for external event counting, and can operate as two independent 8-bit timers, timer FH and timer FL. Features Features of timer F are given below. * Choice of four internal clock sources (/32, /16, /4, /2) or an external clock (can be used as an external event counter). * Output from pin TMOFH is toggled by one compare match signal (the initial value of the toggle output can be set). * Counter can be reset by the compare match signal. * Two interrupt sources: counter overflow and compare match. * Can operate as two independent 8-bit timers (timer FH and timer FL) in 8-bit mode. Rev.3.00 Jul. 19, 2007 page 226 of 532 REJ09B0397-0300 9. Timers Timer FH * 8-bit timer (clocked by timer FL overflow signals when timer F operates as a 16-bit timer). * Choice of four internal clocks (/32, /16, /4, /2). * Output from pin TMOFH is toggled by one compare match signal (the initial value of the toggle output can be set). * Counter can be reset by the compare match signal. * Two interrupt sources: counter overflow and compare match. Timer FL * 8-bit timer/event counter * Choice of four internal clocks (/32, /16, /4, /2) or event input at pin TMIF. * Output from pin TMOFL is toggled by one compare match signal (the initial value of the toggle output can be set). * Counter can be reset by the compare match signal. * Two interrupt sources: counter overflow and compare match. Rev.3.00 Jul. 19, 2007 page 227 of 532 REJ09B0397-0300 9. Timers Block Diagram Figure 9.4 shows a block diagram of timer F. PSS IRRTFL TCRF TMIF TMOFL Toggle circuit TCFL Compare circuit Internal data bus OCRFL TCFH Toggle circuit TMOFH Compare circuit Match OCRFH TCSRF Legend: TCRF: TCSRF: TCFH: TCFL: OCRFH: OCRFL: IRRTFH: IRRTFL: PSS: Timer control register F Timer control status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Timer FH interrupt request flag Timer FL interrupt request flag Prescaler S IRRTFH Figure 9.4 Block Diagram of Timer F Rev.3.00 Jul. 19, 2007 page 228 of 532 REJ09B0397-0300 9. Timers Pin Configuration Table 9.11 shows the timer F pin configuration. Table 9.11 Pin Configuration Name Timer F event input Timer FH output Timer FL output Abbr. TMIF TMOFH TMOFL I/O Input Output Output Function Event input to TCFL Timer FH toggle output Timer FL toggle output Register Configuration: Table 9.12 shows the register configuration of timer F. Table 9.12 Timer F Registers Name Timer control register F Timer control/status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Abbr. TCRF TCSRF TCFH TCFL OCRFH OCRFL R/W W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'FF H'FF Address H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB 9.5.2 Register Descriptions 16-Bit Timer Counter (TCF) 8-Bit Timer Counter (TCFH) 8-Bit Timer Counter (TCFL) TCF Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL Rev.3.00 Jul. 19, 2007 page 229 of 532 REJ09B0397-0300 9. Timers TCF is a 16-bit read/write up-counter consisting of two cascaded 8-bit timer counters, TCFH and TCFL. TCF can be used as a 16-bit counter, with TCFH as the upper 8 bits and TCFL as the lower 8 bits of the counter, or TCFH and TCFL can be used as independent 8-bit counters. TCFH and TCFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP). For details see section 9.5.3, Interface with the CPU. Upon reset, TCFH and TCFL are each initialized to H'00. * 16-bit mode (TCF) 16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The TCF input clock is selected by TCRF bits CKSL2 to CKSL0. TCFH can be cleared by a compare match signal. This designation is made in bit CCLRH in TCSRF. When TCF overflows from H'FFFF to H'0000, the overflow flag (OVFH) in TCSRF is set to 1. If bit OVIEH in TCSRF is set to 1 when an overflow occurs, bit IRRTFH in interrupt request register 2 (IRR2) will be set to 1; and if bit IENTFH in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt will be requested. * 8-bit mode (TCFH, TCFL) When bit CKSH2 in timer control register F (TCRF) is set to 1, timer F functions as two separate 8-bit counters, TCFH and TCFL. The TCFH (TCFL) input clock is selected by TCRF bits CKSH2 to CKSH0 (CKSL2 to CKSL0). TCFH (TCFL) can be cleared by a compare match signal. This designation is made in bit CCLRH (CCLRL) in TCSRF. When TCFH (TCFL) overflows from H'FF to H'00, the overflow flag OVFH (OVFL) in TCSRF is set to 1. If bit OVIEH (OVIEL) in TCSRF is set to 1 when an overflow occurs, bit IRRTFH (IRRTHL) in interrupt request register 2 (IRR2) will be set to 1; and if bit IENTFH (IENTFL) in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt will be requested. Rev.3.00 Jul. 19, 2007 page 230 of 532 REJ09B0397-0300 9. Timers 16-Bit Output Compare Register (OCRF) 8-Bit Output Compare Register (OCRFH) 8-Bit Output Compare Register (OCRFL) OCRF Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRFH OCRFL OCRF is a 16-bit read/write output compare register consisting of two 8-bit read/write registers OCRFH and OCRFL. It can be used as a 16-bit output compare register, with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits of the register, or OCRFH and OCRFL can be used as independent 8-bit registers. OCRFH and OCRFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP). For details see section 9.5.3, Interface with the CPU. Upon reset, OCRFH and OCRFL are each initialized to H'FF. * 16-bit mode (OCRF) 16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The OCRF contents are always compared with the 16-bit timer counter (TCF). When the contents match, the compare match flag (CMFH) in TCSRF is set to 1. Also, IRRTFH in interrupt request register 2 (IRR2) is set to 1. If bit IENTFH in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Output for pin TMOFH can be toggled by compare match. The output level can also be set to high or low by bit TOLH of timer control register F (TCRF). * 8-bit mode (OCRFH, OCRFL) Setting bit CKSH2 in TCRF to 1 results in two 8-bit registers, OCRFH and OCRFL. The OCRFH contents are always compared with TCFH, and the OCRFL contents are always compared with TCFL. When the contents match, the compare match flag (CMFH or CMFL) in TCSRF is set to 1. Also, bit IRRTFH (IRRTFL) in interrupt request register 2 (IRR2) set to 1. If bit IENTFH (IENTFL) in interrupt enable register 2 (IENR2) is set to 1 at this time, a CPU interrupt is requested. The output at pin TMOFH (TMOFL) can be toggled by compare match. The output level can also be set to high or low by bit TOLH (TOLL) of the timer control register (TCRF). Rev.3.00 Jul. 19, 2007 page 231 of 532 REJ09B0397-0300 9. Timers Timer Control Register F (TCRF) Bit 7 TOLH Initial value Read/Write 0 W 6 CKSH2 0 W 5 CKSH1 0 W 4 CKSH0 0 W 3 TOLL 0 W 2 CKSL2 0 W 1 CKSL1 0 W 0 CKSL0 0 W TCRF is an 8-bit write-only register. It is used to switch between 16-bit mode and 8-bit mode, to select among four internal clocks and an external clock, and to select the output level at pins TMOFH and TMOFL. Upon reset, TCRF is initialized to H'00. Bit 7--Toggle Output Level H (TOLH): Bit 7 sets the output level at pin TMOFH. The setting goes into effect immediately after this bit is written. Bit 7: TOLH 0 1 Description Low level High level (initial value) Bits 6 to 4--Clock Select H (CKSH2 to CKSH0): Bits 6 to 4 select the input to TCFH from four internal clock signals or the overflow of TCFL. Bit 6: CKSH2 0 1 Bit 5: CKSH1 * 0 Bit 4: CKSH0 * 0 1 1 Legend: * Don't care 0 1 Description 16-bit mode selected. TCFL overflow signals are counted (initial value) Internal clock: /32 Internal clock: /16 Internal clock: /4 Internal clock: /2 Bit 3--Toggle Output Level L (TOLL): Bit 3 sets the output level at pin TMOFL. The setting goes into effect immediately after this bit is written. Bit 3: TOLL 0 1 Description Low level High level (initial value) Rev.3.00 Jul. 19, 2007 page 232 of 532 REJ09B0397-0300 9. Timers Bits 2 to 0--Clock Select L (CKSL2 to CKSL0): Bits 2 to 0 select the input to TCFL from four internal clock signals or external event input. Bit 2: CKSL2 0 1 Bit 1: CKSL1 * 0 Bit 0: CKSL0 * 0 1 1 0 1 Description External event (TMIF). Rising or falling edge is counted*1 (initial value) Internal clock: /32 Internal clock: /16 Internal clock: /4 Internal clock: /2 Legend: * Don't care Note: 1. The edge of the external event signal is selected by bit IEG3 in the IRQ edge select register (IEGR). See section 3.3.2, Interrupt Control Registers for details on the IRQ edge select register. Note that switching the TMIF pin function by changing bit IRQ3 in port mode register 1 (PMR1) from 0 to 1 or from 1 to 0 while the TMIF pin is at the low level may cause the timer F counter to be incremented. Timer Control/Status Register F (TCSRF) Bit 7 OVFH Initial value Read/Write Note: * 0 R/W* 6 CMFH 0 R/W* 5 OVIEH 0 R/W 4 CCLRH 0 R/W 3 OVFL 0 R/W* 2 CMFL 0 R/W* 1 OVIEL 0 R/W 0 CCLRL 0 R/W Only 0 can be written to clear flag. TCSRF is an 8-bit read/write register. It is used for counter clear selection, overflow and compare match indication, and enabling of interrupts caused by timer overflow. Upon reset, TCSRF is initialized to H'00. Bit 7--Timer overflow flag H (OVFH): Bit 7 is a status flag indicating TCFH overflow (H'FF to H'00). This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7: OVFH 0 1 Description Clearing condition: After reading OVFH = 1, cleared by writing 0 to OVFH Setting condition: Set when the value of TCFH goes from H'FF to H'00 (initial value) Rev.3.00 Jul. 19, 2007 page 233 of 532 REJ09B0397-0300 9. Timers Bit 6--Compare Match Flag H (CMFH): Bit 6 is a status flag indicating a compare match between TCFH and OCRFH. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6: CMFH 0 1 Description Clearing condition: After reading CMFH = 1, cleared by writing 0 to CMFH Setting condition: Set when the TCFH value matches OCRFH value (initial value) Bit 5--Timer Overflow Interrupt Enable H (OVIEH): Bit 5 enables or disables TCFH overflow interrupts. Bit 5: OVIEH 0 1 Description TCFH overflow interrupt disabled TCFH overflow interrupt enabled (initial value) Bit 4--Counter Clear H (CCLRH): In 16-bit mode, bit 4 selects whether or not TCF is cleared when a compare match occurs between TCF and OCRF. In 8-bit mode, bit 4 selects whether or not TCFH is cleared when a compare match occurs between TCFH and OCRFH. Bit 4: CCLRH 0 1 Description 16-bit mode: TCF clearing by compare match disabled 8-bit mode: TCFH clearing by compare match disabled 16-bit mode: TCF clearing by compare match enabled 8-bit mode: TCFH clearing by compare match enabled (initial value) Bit 3--Timer Overflow Flag L (OVFL): Bit 3 is a status flag indicating TCFL overflow (H'FF to H'00). This flag is set by hardware and cleared by software. It cannot be set by software. Bit 3: OVFL 0 1 Description Clearing condition: After reading OVFL = 1, cleared by writing 0 to OVFL Setting condition: Set when the value of TCFL goes from H'FF to H'00 (initial value) Rev.3.00 Jul. 19, 2007 page 234 of 532 REJ09B0397-0300 9. Timers Bit 2--Compare Match Flag L (CMFL): Bit 2 is a status flag indicating a compare match between TCFL and OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2: CMFL 0 1 Description Clearing condition: After reading CMFL = 1, cleared by writing 0 to CMFL Setting condition: Set when the TCFL value matches the OCRFL value (initial value) Bit 1--Timer Overflow Interrupt Enable L (OVIEL): Bit 1 enables or disables TCFL overflow interrupts. Bit 1: OVIEL 0 1 Description TCFL overflow interrupt disabled TCFL overflow interrupt enabled (initial value) Bit 0--Counter Clear L (CCLRL): Bit 0 selects whether or not TCFL is cleared when a compare match occurs between TCFL and OCRFL. Bit 0: CCLRL 0 1 Description TCFL clearing by compare match disabled TCFL clearing by compare match enabled (initial value) 9.5.3 Interface with the CPU TCF and OCRF are 16-bit read/write registers, whereas the data bus between the CPU and on-chip peripheral modules has an 8-bit width. For this reason, when the CPU accesses TCF or OCRF, it makes use of an 8-bit temporary register (TEMP). In 16-bit mode, when reading or writing TCF or writing OCRF, always use two consecutive byte size MOV instructions, and always access the upper byte first. Data will not be transferred properly if only the upper byte or only the lower byte is accessed. In 8-bit mode there is no such restriction on the order of access. Write Access: When the upper byte is written, the upper-byte data is loaded into the TEMP register. Next when the lower byte is written, the data in TEMP goes to the upper byte of the register, and the lower-byte data goes directly to the lower byte of the register. Figure 9.5 shows a TCF write operation when H'AA55 is written to TCF. Rev.3.00 Jul. 19, 2007 page 235 of 532 REJ09B0397-0300 9. Timers Upper byte write Bus interface CPU (H'AA) Internal data bus TEMP (H'AA) TCFH ( ) Lower byte write TCFL ( ) Bus interface CPU (H'55) Internal data bus TEMP (H'AA) TCFH (H'AA) TCFL (H'55) Figure 9.5 TCF Write Operation (CPU TCF) Read Access: When the upper byte of TCF is read, the upper-byte data is sent directly to the CPU, and the lower byte is loaded into TEMP. Next when the lower byte is read, the lower byte in TEMP is sent to the CPU. Rev.3.00 Jul. 19, 2007 page 236 of 532 REJ09B0397-0300 9. Timers When the upper byte of OCRF is read, the upper-byte data is sent directly to the CPU. Next when the lower byte is read, the lower-byte data is sent directly to the CPU. Figure 9.6 shows a TCF read operation when H'AAFF is read from TCF. Upper byte read Bus interface CPU (H'AA) Internal data bus TEMP (H'FF) TCFH (H'AA) Lower byte read Bus interface TCFL (H'FF) CPU (H'FF) Internal data bus TEMP (H'FF) TCFH (AB)* TCFL (00)* Note: * Becomes H'AB00 if counter is incremented once. Figure 9.6 TCF Read Operation (TCF CPU) Rev.3.00 Jul. 19, 2007 page 237 of 532 REJ09B0397-0300 9. Timers 9.5.4 Timer Operation Timer F is a 16-bit timer/counter that increments with each input clock. The value set in output compare register F is constantly compared with the value of timer counter F, and when they match the counter can be cleared, an interrupt can be requested, and the port output can be toggled. Timer F can also be used as two independent 8-bit timers. Timer F Operation: Timer F can operate in either 16-bit timer mode or 8-bit timer mode. These modes are described below. * 16-bit timer mode Timer F operates in 16-bit timer mode when the CKSH2 bit in timer control register F (TCRF) is cleared to 0. A reset initializes timer counter F (TCF) to H'0000, output compare register F (OCRF) to H'FFFF, and timer control register F (TCRF) and timer control status register F (TCSRF) to H'00. Timer F begins counting external event input signals (TMIF). The edge of the external event signal is selected by the IEG3 bit in the IRQ edge select register (IEGR). Any of four internal clocks output by prescaler S, or an external clock, can be selected as the timer F operating clock by bits CKSL2 to CKSL0 in TCRF. TCF is continuously compared with the contents of OCRF. When these two values match, the CMFH bit in TCSRF is set to 1. At this time if IENTFH of IENR2 is 1, a CPU interrupt is requested and the output at pin TMOFH is toggled. If the CCLRH bit in TCSRF is 1, timer F is cleared. The output at pin TMOFH can also be set by the TOLH bit in TCRF. If timer F overflows (from H'FFFF to H'0000), the OVFH bit in TCSRF is set. At this time, if the OVIEH bit in TCSRF and the IENTFH bit in IENR2 are both 1, a CPU interrupt is requested. * 8-bit timer mode When the CKSH2 bit in TCRF is set to 1, timer F operates as two independent 8-bit timers, TCFH and TCFL. The input clock of TCFH/TCFL is selected by bits CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When TCFH/TCFL and the contents of OCRFH/OCRFL match, the CMFH/CMFL bit in TCSRF is set to 1. If the IENTFH/IENTFL bit in IENR2 is 1, a CPU interrupt is requested and the output at pin TMOFH/TMOFL is toggled. If the CCLRH/CCLRL bit in TCRF is 1, TCFH/TCFL is cleared. The output at pin TMOFH/TMOFL can also be set by the TOLH/TOLL bit in TCRF. When TCFH/TCFL overflows from H'FF to H'00, the OVFH/OVFL bit in TCSRF is set to 1. At this time, if the OVIEH/OVIEL bit in TCSRF and the IENTFH/IENTFL bit in IENR2 are both 1, a CPU interrupt is requested. Rev.3.00 Jul. 19, 2007 page 238 of 532 REJ09B0397-0300 9. Timers TCF Count Timing: TCF is incremented by each pulse of the input clock (internal or external clock). * Internal clock The settings of bits CKSH2 to CKSH0 or bits CKSL2 to CKSL0 in TCRF select one of four internal clock signals divided from the system clock (), namely, /32, /16, /4, or /2. * External clock External clock input is selected by clearing bit CKSL2 to 0 in TCRF. Either rising or falling edges of the clock input can be counted. The edge of an external event is selected by bit IEG3 in the interrupt controller's IEGR register. An external event pulse width of at least two system clock () cycles is necessary for correct operation of the counter. TMOFH and TMOFL Output Timing: The outputs at pins TMOFH and TMOFL are the values set in bits TOLH and TOLL in TCRF. When a compare match occurs, the output value is inverted. Figure 9.7 shows the output timing. TMIF (when IEG3 = 1) Count input clock TCF N N+1 N N+1 OCRF N N Compare match signal TMOFH, TMOFL Figure 9.7 TMOFH, TMOFL Output Timing TCF Clear Timing: TCF can be cleared at compare match with OCRF. Rev.3.00 Jul. 19, 2007 page 239 of 532 REJ09B0397-0300 9. Timers Timer Overflow Flag (OVF) Set Timing: OVF is set to 1 when TCF overflows (goes from H'FFFF to H'0000). Compare Match Flag Set Timing: The compare match flags (CMFH or CMFL) are set to 1 when a compare match occurs between TCF and OCRF. A compare match signal is generated in the final state in which the values match (when TCF changes from the matching count value to the next value). When TCF and OCRF match, a compare match signal is not generated until the next counter clock pulse. Timer F Operation States: Table 9.13 summarizes the timer F operation states. Table 9.13 Timer F Operation States Operation Mode TCF OCRF TCRF TCSRF Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Sleep Functions Retained Retained Retained Watch Halted Retained Retained Retained Subactive Halted Retained Retained Retained Subsleep Halted Retained Retained Retained Standby Halted Retained Retained Retained 9.5.5 Application Notes The following conflicts can arise in timer F operation. * 16-bit timer mode The output at pin TMOFH toggles when all 16 bits match and a compare match signal is generated. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH. The TMOFL output in 16-bit mode is indeterminate, so this output should not be used. Use the pin as a general input or output port. If an OCRFL write occurs at the same time as a compare match signal, the compare match signal is inhibited. If a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated; bit CMFL is set when the setting conditions are met for the lower 8 bits. The overflow flag (OVFH) is set when TCF overflows; bit OVFL is set if the setting conditions are met when the lower 8 bits overflow. If a write to TCFL occurs at the same time as an overflow signal, the overflow signal is not output. Rev.3.00 Jul. 19, 2007 page 240 of 532 REJ09B0397-0300 9. Timers * 8-bit timer mode TCFH and OCRFH The output at pin TMOFH toggles when there is a compare match. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH. If an OCRFH write occurs at the same time as a compare match signal, the compare match signal is inhibited. If a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFH clock. If a TCFH write occurs at the same time as an overflow signal, the overflow signal is not output. TCFL and OCRFL The output at pin TMOFL toggles when there is a compare match. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLL will be output at pin TMOFL. If an OCRFL write occurs at the same time as a compare match signal, the compare match signal is inhibited. If a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. If a TCFL write occurs at the same time as an overflow signal, the overflow signal is not output. 9.6 9.6.1 Watchdog Timer [H8/3857F and H8/3854F Only] Overview The watchdog timer (WDT) is equipped with an 8-bit counter that is incremented by an input clock. An internal chip reset can be executed if the counter overflows because it is not updated normally due to a system crash, etc. This watchdog timer is used by the flash memory programming control program. Features Features of the watchdog timer are given below. * Choice of eight internal clock sources (/64, /128, /256, /512, /1024, /2048, /4096, /8192) * Reset signal generated on counter overflow Rev.3.00 Jul. 19, 2007 page 241 of 532 REJ09B0397-0300 9. Timers An overflow period of 1 to 256 times the selected clock can be set. Block Diagram Figure 9.8 shows a block diagram of the watchdog timer. TCSRW Internal data bus PSS TCW TMW Internal reset signal Legend: TCSRW TCW PSS TMW : Timer control/status register W : Timer counter W : Prescaler S : Timer mode register W Figure 9.8 Block Diagram of Watchdog Timer Register Configuration Table 9.14 shows the watchdog timer register configuration. These registers are valid only in the F-ZTAT version. In the mask ROM version, read accesses to the corresponding addresses will always return 1, and writes are invalid. Table 9.14 Watchdog Timer Registers Name Timer control/status register W Timer counter W Timer mode register W Abbr. TCSRW TCW TMW R/W R/W R/W R/W Initial Value H'AA H'00 H'FF Address H'FF90 H'FF91 H'FF92 Rev.3.00 Jul. 19, 2007 page 242 of 532 REJ09B0397-0300 9. Timers 9.6.2 Register Descriptions Timer Control/Status Register W (TCSRW) Bit Initial value Read/Write 7 B6WI 6 TCWE 5 B4WI 4 TCSRWE 3 B2WI 2 WDON 1 BOWI 0 WRST 1 R 0 R/(W)* 1 R 0 R/(W)* 1 R 0 R/(W)* 1 R 0 R/(W)* Note: * Can be written to only when the write condition is satisfied. For the write conditions, see the individual bit descriptions. TCSRW is an 8-bit read/write register that performs TCSRW and TCW write control and watchdog timer operation control, and indicates the operation status. Bit 7--Bit 6 Write Inhibit (B6WI): Bit 7 controls writing of data to bit 6 of TCSRW. Bit 7: B6WI 0 1 Description Writing to bit 6 is enabled Writing to bit 6 is disabled (initial value) This bit is always read as 1. Data is not stored if written to this bit. Bit 6--Timer Counter W Write Enable (TCWE): Bit 6 controls writing of 8-bit data to TCW. Bit 6: TCWE Description 0 1 Writing of 8-bit data to TCW is disabled Writing of 8-bit data to TCW is enabled (initial value) Bit 5--Bit 4 Write Inhibit (B4WI): Bit 5 controls writing of data to bit 4 of TCSRW. Bit 5: B4WI 0 1 Description Writing to bit 4 is enabled Writing to bit 4 is disabled (initial value) This bit is always read as 1. Data is not stored if written to this bit. Rev.3.00 Jul. 19, 2007 page 243 of 532 REJ09B0397-0300 9. Timers Bit 4--Timer Control/Status Register W Write Enable (TCSRWE): Bit 4 controls writing of data to bits 2 and 0 of TCSRW. Bit 4: TCSRWE Description 0 1 Writing to bits 2 and 0 is disabled Writing to bits 2 and 0 is enabled (initial valu Bit 3--Bit 2 Write Inhibit (B2WI): Bit 3 controls writing of data to bit 2 of TCSRW. Bit 3: B2WI 0 1 Description Writing to bit 2 is enabled Writing to bit 2 is disabled (initial value) This bit is always read as 1. Data is not stored if written to this bit. Bit 2--Watchdog Timer On (WDON): Bit 2 controls watchdog timer operation. Bit 2: WDON Description 0 Watchdog timer operation is disabled [Clearing condition] In a reset, or when 0 is written to WDON while writing 0 to B2WI when TCSRWE = 1 1 Watchdog timer operation is enabled [Setting condition] When 1 is written to WDON while writing 0 to B2WI when TCSRWE = 1 (initial value) The count-up starts when this bit is set to 1, and stops when it is cleared to 0. Bit 1--Bit 0 Write Inhibit (B0WI): Bit 1 controls writing of data to bit 0 of timer control/status register W. Bit 1: B0WI 0 1 Description Writing to bit 0 is enabled Writing to bit 0 is disabled (initial value) This bit is always read as 1. Data is not stored if written to this bit. Rev.3.00 Jul. 19, 2007 page 244 of 532 REJ09B0397-0300 9. Timers Bit 0--Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed and an internal reset signal has been generated. The internal reset signal generated by the overflow resets the entire chip. WRST is cleared by a reset via the RES pin or by a 0 write by software. Bit 0: WRST Description 0 [Clearing conditions] * * 1 Reset by RES pin When 0 is written to WRST while writing 0 to B0WI when TCSRWE = 1 (initial value) [Setting condition] When TCW overflows and an internal reset signal is generated Timer Counter W (TCW) Bit Initial value Read/Write 7 TCW7 6 TCW6 5 TCW5 4 TCW4 3 TCW3 2 TCW2 1 TCW1 0 TCW0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCW is an 8-bit read/write up-counter that is incremented by an input internal clock. The TCW value can be read or written by the CPU at any time. When TCW overflows (from H'FF to H'00), an internal reset signal is generated and WRST in TCSRW is set to 1. Upon reset, TCW is initialized to H'00. Timer Mode Register W (TMW) Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 2 CKS2 1 CKS1 0 CKS0 1 R/W 1 R/W 1 R/W TMW is an 8-bit read/write register that selects the input clock. Upon reset, TMW is initialized to H'FF. Bits 7 to 3--Reserved Bits: Bits 7 to 3 are reserved; they are always read as 1 and cannot be modified. Rev.3.00 Jul. 19, 2007 page 245 of 532 REJ09B0397-0300 9. Timers Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 select the clock to be input to TCW. Bit 2: CKS2 0 Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: /64 Internal clock: /128 Internal clock: /256 Internal clock: /512 Internal clock: /1024 Internal clock: /2048 Internal clock: /4096 Internal clock: /8192 (initial value) 9.6.3 Operation The watchdog timer is provided with an 8-bit counter that increments with each input clock pulse. If 1 is written to WDON while writing 0 to B2WI when TCSRWE in TCSRW is set to 1, TCW begins counting up. When a clock pulse is input after the TCW count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated one base clock () cycle later. The internal reset signal is output for a period of 512 osc clock cycles. TCW is a writable counter, and when a value is set in TCW, the count-up starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCW value. Figure 9.9 shows an example of watchdog timer operation. Rev.3.00 Jul. 19, 2007 page 246 of 532 REJ09B0397-0300 9. Timers Example: With 30 ms overflow period when = 4 MHz (/8192 selected) 4 x 106 8192 x 30 x 10-3 = 14.6 Therefore, 256 - 15 = 241 (H'F1) is set in TCW. TCW overflow H'FF H'F1 TCW count value H'00 Start H'F1 written to TCW Internal reset signal H'F1 written to TCW Reset generated 512 osc clock cycles Figure 9.9 Example of Watchdog Timer Operation 9.6.4 Watchdog Timer Operating Modes Watchdog timer operating modes are shown in table 9.15. Table 9.15 Watchdog Timer Operating Modes Operating mode Reset TCW TCSRW TMW Reset Reset Reset Active Functions Functions Functions Sleep Functions Functions Retained Watch Halted Retained Retained Subactive Subsleep Halted Retained Retained Halted Retained Retained Standby Halted Retained Retained Rev.3.00 Jul. 19, 2007 page 247 of 532 REJ09B0397-0300 9. Timers Rev.3.00 Jul. 19, 2007 page 248 of 532 REJ09B0397-0300 10. Serial Communication Interface Section 10 Serial Communication Interface 10.1 Overview The H8/3857 Group is provided with a two-channel serial communication interface (SCI), and the H8/3854 Group with a single-channel SCI. Table 10.1 summarizes the functions and features of the SCI channels. Table 10.1 Serial Communication Interface Functions Channel SCI1* Functions Synchronous serial transfer * * SCI3 Choice of 8-bit or 16-bit data length Continuous clock output Features * * * * * * * Choice of 8 internal clocks (/1024 to /2) or external clock Open drain output possible Interrupt requested at completion of transfer Built-in baud rate generator Receive error detection Break detection Interrupt requested at completion of transfer or error Synchronous serial transfer * * 8-bit data transfer Send, receive, or simultaneous send/receive Asynchronous serial transfer * * * * Multiprocessor communication function Choice of 7-bit or 8-bit data length Choice of 1-bit or 2-bit stop bit length Parity addition Note: * SCI1 is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. Rev.3.00 Jul. 19, 2007 page 249 of 532 REJ09B0397-0300 10. Serial Communication Interface 10.2 10.2.1 SCI1 (H8/3857 Group Only) Overview Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit data. SCI1 is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. Features Features of SCI1 are as follows. * Choice of 8-bit or 16-bit transfer data length * Choice of eight internal clock sources (/1024, /256, /64, /32, /16, /8, /4, /2) or an external clock * Interrupt requested at completion of transfer Rev.3.00 Jul. 19, 2007 page 250 of 532 REJ09B0397-0300 10. Serial Communication Interface Block Diagram Figure 10.1 shows a block diagram of SCI1. PSS SCK1 SCR1 Transfer bit counter SI1 SDRU SDRL SO1 IRRS1 Legend: SCR1: SCSR1: SDRU: SDRL: IRRS1: PSS: Serial control register 1 Serial control/status register 1 Serial data register U Serial data register L SCI1 interrupt request flag Prescaler S Figure 10.1 SCI1 Block Diagram Rev.3.00 Jul. 19, 2007 page 251 of 532 REJ09B0397-0300 Internal data bus Transmit/receive control circuit SCSR1 10. Serial Communication Interface Pin Configuration Table 10.2 shows the SCI1 pin configuration. Table 10.2 Pin Configuration Name SCI1 clock pin SCI1 data input pin SCI1 data output pin Abbr. SCK1 SI1 SO1 I/O I/O Input Output Function SCI1 clock input or output SCI1 receive data input SCI1 transmit data output Register Configuration Table 10.3 shows the SCI1 register configuration. Table 10.3 SCI1 Registers Name Serial control register 1 Serial control status register 1 Serial data register U Serial data register L Abbr. SCR1 SCSR1 SDRU SDRL R/W R/W R/W R/W R/W Initial Value H'00 H'80 Undefined Undefined Address H'FFA0 H'FFA1 H'FFA2 H'FFA3 10.2.2 Register Descriptions Serial Control Register 1 (SCR1) Bit 7 SNC1 Initial value Read/Write 0 R/W 6 SNC0 0 R/W 5 0 R/W 4 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCR1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source, and the prescaler division ratio. Upon reset, SCR1 is initialized to H'00. Writing to this register during a transfer stops the transfer. Rev.3.00 Jul. 19, 2007 page 252 of 532 REJ09B0397-0300 10. Serial Communication Interface Bits 7 and 6--Operation Mode Select 1, 0 (SNC1, SNC0): Bits 7 and 6 select the operation mode. Bit 7: SNC1 0 Bit 6: SNC0 0 1 1 0 1 Description 8-bit synchronous transfer mode 16-bit synchronous transfer mode Continuous clock output mode*1 Reserved*2 (initial value) Notes: 1. Pins SI1 and SO1 should be used as general input or output ports. 2. Don't set bits SNC1 and SNC0 to 11. Bits 5 and 4--Reserved Bits: Bits 5 and 4 are reserved; they should always be cleared to 0. Bit 3--Clock Source Select 3 (CKS3): Bit 3 selects the clock source and sets pin SCK1 as an input or output pin. Bit 3: CKS3 0 1 Description Clock source is prescaler S, and pin SCK1 is output pin Clock source is external clock, and pin SCK1 is input pin (initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS 0): When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. Serial Clock Cycle Bit 2: CKS2 0 Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Prescaler Division /1024 (initial value) /256 /64 /32 /16 /8 /4 /2 = 5 MHz 204.8 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s = 2.5 MHz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s Rev.3.00 Jul. 19, 2007 page 253 of 532 REJ09B0397-0300 10. Serial Communication Interface Serial Control/Status Register 1 (SCSR1) Bit 7 Initial value Read/Write Note: * 1 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 0 3 0 2 0 1 0 R/W 0 STF 0 R/W Only a write of 0 for flag clearing is possible. SCSR1 is an 8-bit read/write register indicating operation status and error status. Upon reset, SCSR1 is initialized to H'80. Do not read or write to SCSR1 during a transfer operation, as this will cause erroneous operation. Bit 7--Reserved Bit: Bit 7 is reserved; it is always read as 1, and cannot be modified. Bit 6--Extended Data Bit (SOL): Bit 6 sets the SO1 output level. When read, SOL returns the output level at the SO1 pin. After completion of a transmission, SO1 continues to output the value of the last bit of transmitted data. The SO1 output can be changed by writing to SOL before or after a transmission. The SOL bit setting remains valid only until the start of the next transmission. To control the level of the SO1 pin after transmission ends, it is necessary to write to the SOL bit at the end of each transmission. Do not write to this register while transmission is in progress, because that may cause a malfunction. Bit 6: SOL 0 Description Read: SO1 pin output level is low Write: SO1 pin output level changes to low 1 Read: SO1 pin output level is high Write: SO1 pin output level changes to high (initial value) Rev.3.00 Jul. 19, 2007 page 254 of 532 REJ09B0397-0300 10. Serial Communication Interface Bit 5--Overrun Error Flag (ORER): When an external clock is used, bit 5 indicates the occurrence of an overrun error. If a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. If noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. Bit 5: ORER 0 1 Description Clearing condition: After reading ORER = 1, cleared by writing 0 to ORER (initial value) Setting condition: Set if a clock pulse is input after transfer is complete, when an external clock is used Bits 4 to 2--Reserved Bits: Bits 4 to 2 are reserved; they are always read as 0, and cannot be modified. Bit 1--Reserved Bit: Bit 1 is reserved; it should always be cleared to 0. Bit 0--Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to start transferring data. This bit remains set to 1 during transfer or while waiting for a start bit, and is cleared to 0 upon completion of the transfer. Bit 0: STF 0 Description Read: Indicates that transfer is stopped Write: Invalid 1 Read: Indicates transfer in progress Write: Starts a transfer operation (initial value) Serial Data Register U (SDRU) Bit 7 SDRU7 Initial value Read/Write R/W 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3 SDRU3 R/W 2 SDRU2 R/W 1 SDRU1 R/W 0 SDRU0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit transfer (SDRL is used for the lower 8 bits). Rev.3.00 Jul. 19, 2007 page 255 of 532 REJ09B0397-0300 10. Serial Communication Interface Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. SDRU must be written or read only after data transmission or reception is complete. If this register is written or read while a data transfer is in progress, the data contents are not guaranteed. The SDRU value upon reset is not fixed. Serial Data Register L (SDRL) Bit 7 SDRL7 Initial value Read/Write R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 SDRL3 R/W 2 SDRL2 R/W 1 SDRL1 R/W 0 SDRL0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits). In 8-bit transfer, data written to SDRL is output from pin SO1 starting from the least significant bit (LSB). This data is than replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via SDRU. SDRL must be written or read only after data transmission or reception is complete. If this register is read or written while a data transfer is in progress, the data contents are not guaranteed. The SDRL value upon reset is not fixed. 10.2.3 Operation Data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external serial clock. Overrun errors can be detected when an external clock is used. Clock The serial clock can be selected from a choice of eight internal clocks and an external clock. When an internal clock source is selected, pin SCK1 becomes the clock output pin. When continuous clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock signal (/1024 Rev.3.00 Jul. 19, 2007 page 256 of 532 REJ09B0397-0300 10. Serial Communication Interface to /2) selected in bits CKS2 to CKS0 is output continuously from pin SCK1. When an external clock is used, pin SCK1 is the clock input pin. Data Transfer Format Figure 10.2 shows the data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial clock until the next falling edge. Receive data is latched at the rising edge of the serial clock. SCK 1 SO1 /SI 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 10.2 Transfer Format Data Transfer Operations Transmitting: A transmit operation is carried out as follows. * Set bits SO1 and SCK1 in PMR3 TO 1 so that the respective pins function as SO1 and SCK1. If necessary, set bit POF1 in port mode register 2 (PMR2) for NMOS open drain output at pin SO1. * Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes the internal state of SCI1. * Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL * Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin SO1. * After data transmission is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. When an external clock is used, data is transmitted in synchronization with the serial clock input at pin SCK1. After data transmission is complete, an overrun occurs if the serial clock continues to be input; no data is transmitted and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1. Rev.3.00 Jul. 19, 2007 page 257 of 532 REJ09B0397-0300 10. Serial Communication Interface Receiving: A receive operation is carried out as follows. * Set bits SI1 and SCK1 in PMR3 to 1 so that the respective pins function as SI1 and SCK1. * Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes the internal state of SCI1. * Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and receives data at pin SI1. * After data reception is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. * Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL * After data reception is complete, an overrun occurs if the serial clock continues to be input; no data is received and the SCSR1 overrun error flag (bit ORER) is set to 1. Simultaneous transmit/receive: A simultaneous transmit/receive operation is carried out as follows. * Set bits SO1, SI1, and SCK1 in PMR3 to 1 so that the respective pins function as SO1, SI1, and SCK1. If necessary, set bit POF1 in port mode register 2 (PMR2) for NMOS open drain output at pin SO1. * Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes the internal state of SCI1. * Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL * Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO1. Receive data is input at pin SI1. * After data transmission and reception are complete, bit IRRS1 in IRR1 is set to 1. * Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. Rev.3.00 Jul. 19, 2007 page 258 of 532 REJ09B0397-0300 10. Serial Communication Interface When an external clock is used, data is transmitted and received in synchronization with the serial clock input at pin SCK1. After data transmission and reception are complete, an overrun occurs if the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1. 10.2.4 Interrupts SCI1 can generate an interrupt at the end of a data transfer. When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 1 (IENR1). For further details, see section 3.3, Interrupts. 10.2.5 Application Notes Note the following points when using SCI1. When an External Clock is Input to the SCK1 Pin: When SCK1 is designated as an input pin and an external clock is selected as the clock source, do not input the external clock before writing 1 to the STF bit in SCSR1 to start the transfer operation. Confirming the End of Serial Transfer: Do not read or write to SCSR1 during serial transfer. The following two methods can be used to confirm the end of serial transfer: * Using SCI1 interrupt exception handling Set the IENS1 bit to 1 in IENR1 and execute interrupt exception handling. * Using IRR1 polling With SCI1 interrupts disabled (IENS1 = 0 in IENR1), confirm that the IRRS1 bit in IRR1 has been set to 1. Rev.3.00 Jul. 19, 2007 page 259 of 532 REJ09B0397-0300 10. Serial Communication Interface 10.3 10.3.1 SCI3 Overview Serial communication interface 3 (SCI3) has both synchronous and asynchronous serial data communication capabilities. It also has a multiprocessor communication function for serial data communication among two or more processors. Features SCI3 features are listed below. * Selection of asynchronous or synchronous mode Asynchronous mode Serial data communication is performed using an asynchronous method in which synchronization is established character by character. SCI3 can communicate with a UART (universal asynchronous receiver/transmitter), ACIA (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. * Data length: seven or eight bits * Stop bit length: one or two bits * Parity: even, odd, or none * Multiprocessor bit: one or none * Receive error detection: parity, overrun, and framing errors * Break detection: by reading the RXD level directly when a framing error occurs Synchronous mode Serial data communication is synchronized with a clock signal. SCI3 can communicate with other chips having a clocked synchronous communication function. * Data length: eight bits * Receive error detection: overrun errors * Full duplex communication The transmitting and receiving sections are independent, so SCI3 can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * Built-in baud rate generator with selectable bit rates. * Internal or external clock may be selected as the transfer clock source. Rev.3.00 Jul. 19, 2007 page 260 of 532 REJ09B0397-0300 10. Serial Communication Interface * There are six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error. Block Diagram Figure 10.3 shows a block diagram of SCI3. External clock Baud rate generator BRC Clock SMR Transmit/receive control SCR3 SSR Internal data bus SCK 3 Internal clock (/64, /16, /4, ) BRR TXD TSR TDR RXD RSR RDR Interrupt requests (TEI, TXI, RXI, ERI) Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR3: Serial control register 3 SSR: Serial status register BRR: Bit rate register BRC: Bit rate counter Figure 10.3 SCI3 Block Diagram Rev.3.00 Jul. 19, 2007 page 261 of 532 REJ09B0397-0300 10. Serial Communication Interface Pin Configuration Table 10.4 shows the SCI3 pin configuration. Table 10.4 Pin Configuration Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbr. SCK3 RXD TXD I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output Register Configuration Table 10.5 shows the SCI3 internal register configuration. Table 10.5 SCI3 Registers Name Serial mode register Bit rate register Serial control register 3 Transmit data register Serial status register Receive data register Transmit shift register Receive shift register Bit rate counter Legend: : Cannot be read or written. Abbr. SMR BRR SCR3 TDR SSR RDR TSR RSR BRC R/W R/W R/W R/W R/W R/W R * * * Initial Value H'00 H'FF H'00 H'FF H'84 H'00 Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD 10.3.2 Register Descriptions Receive Shift Register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write Rev.3.00 Jul. 19, 2007 page 262 of 532 REJ09B0397-0300 10. Serial Communication Interface The receive shift register (RSR) is for receiving serial data. Serial data is input in LSB (bit 0) order into RSR from pin RXD, converting it to parallel data. After each byte of data has been received, the byte is automatically transferred to the receive data register (RDR). RSR cannot be read or written directly by the CPU. Receive Data Register (RDR) Bit 7 RDR7 Initial value Read/Write 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R 2 RDR2 0 R 1 RDR1 0 R 0 RDR0 0 R The receive data register (RDR) is an 8-bit register for storing received serial data. Each time a byte of data is received, the received data is transferred from the receive shift register (RSR) to RDR, completing a receive operation. Thereafter RSR again becomes ready to receive new data. RSR and RDR form a double buffer mechanism that allows data to be received continuously. RDR is exclusively for receiving data and cannot be written by the CPU. RDR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Transmit Shift Register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write The transmit shift register (TSR) is for transmitting serial data. Transmit data is first transferred from the transmit data register (TDR) to TSR, then is transmitted from pin TXD, starting from the LSB (bit 0). After one byte of data has been sent, the next byte is automatically transferred from TDR to TSR, and the next transmission begins. If no data has been written to TDR (1 is set in TDRE), there is no data transfer from TDR to TSR. Rev.3.00 Jul. 19, 2007 page 263 of 532 REJ09B0397-0300 10. Serial Communication Interface TSR cannot be read or written directly by the CPU. Transmit Data Register (TDR) Bit 7 TDR7 Initial value Read/Write 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W 2 TDR2 1 R/W 1 TDR1 1 R/W 0 TDR0 1 R/W The transmit data register (TDR) is an 8-bit register for holding transmit data. When SCI3 detects that the transmit shift register (TSR) is empty, it shifts transmit data written in TDR to TSR and starts serial data transmission. While TSR is transmitting serial data, the next byte to be transmitted can be written to TDR, realizing continuous transmission. TDR can be read or written by the CPU at all times. TDR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Serial Mode Register (SMR) Bit 7 COM Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W The serial mode register (SMR) is an 8-bit register for setting the serial data communication format and for selecting the clock source of the baud rate generator. SMR can be read and written by the CPU at any time. SMR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Bit 7--Communication Mode (COM): Bit 7 selects asynchronous mode or synchronous mode as the serial data communication mode. Bit 7: COM 0 1 Description Asynchronous mode Synchronous mode (initial value) Rev.3.00 Jul. 19, 2007 page 264 of 532 REJ09B0397-0300 10. Serial Communication Interface Bit 6--Character Length (CHR): Bit 6 selects either 7 bits or 8 bits as the data length in asynchronous mode. In synchronous mode the data length is always 8 bits regardless of the setting here. Bit 6: CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected as the character length in asynchronous mode, the MSB (bit 7) in the transmit data register is not transmitted. (initial value) Bit 5--Parity Enable (PE): In asynchronous mode, bit 5 selects whether or not a parity bit is to be added to transmitted data and checked in received data. In synchronous mode there is no adding or checking of parity regardless of the setting here. Bit 5: PE 0 1 Note: * Description Parity bit adding and checking disabled Parity bit adding and checking enabled* When PE is set to 1, then either odd or even parity is added to transmit data, depending on the setting of the parity mode bit (PM). When data is received, it is checked for odd or even parity as designated in bit PM. (initial value) Bit 4--Parity Mode (PM): In asynchronous mode, bit 4 selects whether odd or even parity is to be added to transmitted data and checked in received data. The PM setting is valid only if bit PE is set to 1, enabling parity adding/checking. In synchronous mode, or if parity adding/checking is disabled in asynchronous mode, the PM setting is invalid. Bit 4: PM 0 1 Description Even parity*1 Odd parity* 2 (initial value) Notes: 1. When even parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an even number. When data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an even number. 2. When odd parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an odd number. When data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an odd number. Rev.3.00 Jul. 19, 2007 page 265 of 532 REJ09B0397-0300 10. Serial Communication Interface Bit 3--Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. This setting is valid only in asynchronous mode. In synchronous mode a stop bit is not added, so this bit is ignored. Bit 3: STOP 0 1 Description 1 stop bit*1 2 stop bits* 2 (initial value) Notes: 1. When data is transmitted, one 1 bit is added at the end of each transmitted character as the stop bit. 2. When data is transmitted, two 1 bits are added at the end of each transmitted character as the stop bits. When data is received, only the first stop bit is checked regardless of the stop bit length. If the second stop bit value is 1 it is treated as a stop bit; if it is 0, it is treated as the start bit of the next character. Bit 2--Multiprocessor Mode (MP): Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor communication function is enabled, the parity enable (PE) and parity mode (PM) settings are ignored. The MP bit is valid only in asynchronous mode; it should be cleared to 0 in synchronous mode. See section 10.3.6, Multiprocessor Communication Function for details on the multiprocessor communication function. Bit 2: MP 0 1 Description Multiprocessor communication function disabled Multiprocessor communication function enabled (initial value) Bits 1 and 0--Clock Select 1, 0 (CKS1, CKS0): Bits 1 and 0 select the clock source for the builtin baud rate generator. A choice of /64, /16, /4, or is made in these bits. See Bit Rate Register (BRR) in section 10.3.2, Register Descriptions, below for information on the clock source and bit rate register settings, and their relation to the baud rate. Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description clock /4 clock /16 clock /64 clock (initial value) Rev.3.00 Jul. 19, 2007 page 266 of 532 REJ09B0397-0300 10. Serial Communication Interface Serial Control Register 3 (SCR3) Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Serial control register 3 (SCR3) is an 8-bit register that controls SCI3 transmit and receive operations, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the serial clock source. SCR3 can be read and written by the CPU at any time. SCR3 is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Bit 7--Transmit Interrupt Enable (TIE): Bit 7 enables or disables the transmit data empty interrupt (TXI) request when data is transferred from TDR to TSR and the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1. The TXI interrupt can be cleared by clearing bit TDRE to 0, or by clearing bit TIE to 0. Bit 7: TIE 0 1 Description Transmit data empty interrupt request (TXI) disabled Transmit data empty interrupt request (TXI) enabled (initial value) Bit 6--Receive Interrupt Enable (RIE): Bit 6 enables or disables the receive error interrupt (ERI), and the receive data full interrupt (RXI) requested when data is transferred from RSR to RDR and the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1. There are three kinds of receive error: overrun, framing, and parity. RXI and ERI interrupts can be cleared by clearing SSR flag RDRF, or flags FER, PER, and OER to 0, or by clearing bit RIE to 0. Bit 6: RIE 0 1 Description Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled (initial value) Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled Rev.3.00 Jul. 19, 2007 page 267 of 532 REJ09B0397-0300 10. Serial Communication Interface Bit 5--Transmit Enable (TE): Bit 5 enables or disables the start of a transmit operation. Bit 5: TE 0 1 Description Transmit operation disabled*1 (TXD is a general I/O port) Transmit operation enabled* (TXD is the transmit data pin) 2 (initial value) Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is fixed at 1. 2. In this state, writing transmit data in TDR clears bit TDRE in SSR to 0 and starts serial data transmission. Before setting TE to 1 it is necessary to set the transmit format in SMR. When performing simultaneous transmission and reception in synchronous mode, TE and RE should be set to 1 simultaneously by a single instruction when they are both cleared to 0. Bit 4--Receive Enable (RE): Bit 4 enables or disables the start of a receive operation. Bit 4: RE 0 1 Description Receive operation disabled*1 (RXD is a general I/O port) Receive operation enabled* (RXD is the receive data pin) 2 (initial value) Notes: 1. When RE is cleared to 0, this has no effect on the SSR flags RDRF, FER, PER, and OER, which retain their states. 2. Serial data receiving begins when, in this state, a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. Before setting RE to 1 it is necessary to set the receive format in SMR. When performing simultaneous transmission and reception in synchronous mode, TE and RE should be set to 1 simultaneously by a single instruction when they are both cleared to 0. Bit 3--Multiprocessor Interrupt Enable (MPIE): Bit 3 enables or disables multiprocessor interrupt requests. This setting is valid only in asynchronous mode, and only when the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1. This bit is ignored when COM is set to 1 or when bit MP is cleared to 0. Bit 3: MPIE 0 Description Multiprocessor interrupt request disabled (ordinary receive operation) (initial value) Clearing condition: Multiprocessor bit receives a data value of 1 1 Note: * Multiprocessor interrupt request enabled* SCI3 does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set status flags RDRF, FER, and OER in SSR. Until a multiprocessor bit Rev.3.00 Jul. 19, 2007 page 268 of 532 REJ09B0397-0300 10. Serial Communication Interface value of 1 is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are disabled and serial status register (SSR) flags RDRF, FER, and OER are not set. When the multiprocessor bit receives a 1, the MPBR bit of SSR is set to 1, MPIE is automatically cleared to 0, RXI and ERI interrupts are enabled (provided bits TIE and RIE in SCR3 are set to 1), and setting of the RDRF, FER, and OER flags is enabled. Bit 2--Transmit End Interrupt Enable (TEIE): Bit 2 enables or disables the transmit end interrupt (TEI) requested if there is no valid transmit data in TDR when the MSB is transmitted. Bit 2: TEIE 0 1 Note: * Description Transmit end interrupt (TEI) disabled Transmit end interrupt (TEI) enabled* A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the transmit end bit (TEND) to 0, or by clearing bit TEIE to 0. (initial value) Bits 1 and 0--Clock Enable 1, 0 (CKE1, CKE0): Bits 1 and 0 select the clock source and enable or disable clock output at pin SCK3. The combination of bits CKE1 and CKE0 determines whether pin SCK3 is a general I/O port, a clock output pin, or a clock input pin. Note that the CKE0 setting is valid only when operation is in asynchronous mode using an internal clock (CKE1 = 0). This bit is invalid in synchronous mode or when using an external clock (CKE1 = 1). In synchronous mode and in external clock mode, clear CKE0 to 0. After setting bits CKE1 and CKE0, the operation mode must first be set in the serial mode register (SMR). See table 10.12 in section 10.3.3, Operation, for details on clock source selection. Bit 1: CKE1 0 Bit 0: CKE0 0 Communication Mode Asynchronous Synchronous 0 1 Asynchronous Synchronous 1 0 Asynchronous Synchronous 1 1 Asynchronous Synchronous Clock Source Internal clock Internal clock Internal clock Reserved External clock External clock Reserved Reserved SCK3 Pin Function I/O port*1 Serial clock output*1 Clock output*2 Reserved Clock input*3 Serial clock input Reserved Reserved Notes: 1. Initial value 2. A clock is output with the same frequency as the bit rate. 3. Input a clock with a frequency 16 times the bit rate. Rev.3.00 Jul. 19, 2007 page 269 of 532 REJ09B0397-0300 10. Serial Communication Interface Serial Status Register (SSR) Bit 7 TDRE Initial value Read/Write Note: * 1 R/(W)* 6 RDRF 0 R/(W)* 5 OER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPBR 0 R 0 MPBT 0 R/W Only 0 can be written for flag clearing. The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3 states, and containing the multiprocessor bits. SSR can be read and written by the CPU at any time, but the CPU cannot write a 1 to the status flags TDRE, RDRF, OER, PER, and FER. To clear these flags to 0 it is first necessary to read a 1. Bit 2 (TEND) and bit 1 (MPBR) are read-only bits and cannot be modified. SSR is initialized to H'84 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Bit 7--Transmit Data Register Empty (TDRE): Bit 7 is a status flag indicating that data has been transferred from TDR to TSR. Bit 7: TDRE 0 Description Indicates that transmit data written to TDR has not been transferred to TSR Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE. When data is written to TDR by an instruction. 1 Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR (initial value) Setting conditions: When bit TE in SCR3 is cleared to 0. When data is transferred from TDR to TSR. Rev.3.00 Jul. 19, 2007 page 270 of 532 REJ09B0397-0300 10. Serial Communication Interface Bit 6--Receive Data Register Full (RDRF): Bit 6 is a status flag indicating whether there is receive data in RDR. Bit 6: RDRF 0 Description Indicates there is no receive data in RDR Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF. When data is read from RDR by an instruction. 1 Indicates that there is receive data in RDR Setting condition: When receiving ends normally, with receive data transferred from RSR to RDR Note: If a receive error is detected at the end of receiving, or if bit RE in serial control register 3 (SCR3) is cleared to 0, RDR and RDRF are unaffected and keep their previous states. An overrun error (OER) occurs if receiving of data is completed while bit RDRF remains set to 1. If this happens, receive data will be lost. (initial value) Bit 5--Overrun Error (OER): Bit 5 is a status flag indicating that an overrun error has occurred during data receiving. Bit 5: OER 0 Description Indicates that data receiving is in progress or has been completed*1 (initial value) Clearing condition: After reading OER = 1, cleared by writing 0 to OER 1 Indicates that an overrun error occurred in data receiving*2 Setting condition: When data receiving is completed while RDRF is set to 1 Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, OER is unaffected and keeps its previous state. 2. RDR keeps the data received prior to the overrun; data received after that is lost. While OER is set to 1, data receiving cannot be continued. In synchronous mode, data transmitting cannot be continued either. Rev.3.00 Jul. 19, 2007 page 271 of 532 REJ09B0397-0300 10. Serial Communication Interface Bit 4--Framing Error (FER): Bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving. Bit 4: FER 0 Description Indicates that data receiving is in progress or has been completed*1 (initial value) Clearing condition: After reading FER = 1, cleared by writing 0 to FER 1 Indicates that a framing error occurred in data receiving Setting condition: The stop bit at the end of receive data is checked for a value of 1 and found to be 0*2 Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, FER is unaffected and keeps its previous state. 2. When two stop bits are used only the first stop bit is checked, not the second. When a framing error occurs, receive data is transferred to RDR but RDRF is not set. While FER is set to 1, data receiving cannot be continued. In synchronous mode, data transmitting cannot be continued either. Bit 3--Parity Error (PER): Bit 3 is a status flag indicating that a parity error has occurred during asynchronous receiving. Bit 3: PER 0 Description Indicates that data receiving is in progress or has been completed*1 (initial value) Clearing condition: After reading PER = 1, cleared by writing 0 to PER 1 Indicates that a parity error occurred in data receiving*2 Setting condition: When the sum of 1s in received data plus the parity bit does not match the parity mode bit (PM) setting in the serial mode register (SMR) Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, PER is unaffected and keeps its previous state. 2. When a parity error occurs, receive data is transferred to RDR but RDRF is not set. While PER is set to 1, data receiving cannot be continued. In synchronous mode, data transmitting cannot be continued either. Rev.3.00 Jul. 19, 2007 page 272 of 532 REJ09B0397-0300 10. Serial Communication Interface Bit 2--Transmit End (TEND): Bit 2 is a status flag indicating that TDRE was set to 1 when the last bit of a transmitted character was sent. TEND is a read-only bit and cannot be modified directly. Bit 2: TEND 0 Description Indicates that transmission is in progress Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE. When data is written to TDR by an instruction. 1 Indicates that a transmission has ended (initial value) Setting conditions: When bit TE in SCR3 is cleared to 0. If TDRE is set to 1 when the last bit of a transmitted character is sent. Bit 1--Multiprocessor Bit Receive (MPBR): Bit 1 holds the multiprocessor bit in data received in asynchronous mode using a multiprocessor format. MPBR is a read-only bit and cannot be modified. Bit 1: MPBR 0 1 Note: * Description Indicates reception of data in which the multiprocessor bit is 0* Indicates reception of data in which the multiprocessor bit is 1 If bit RE is cleared to 0 while a multiprocessor format is in use, MPBR retains its previous state. (initial value) Bit 0--Multiprocessor Bit Transmit (MPBT): Bit 0 holds the multiprocessor bit to be added to transmitted data when a multiprocessor format is used in asynchronous mode. Bit MPBT is ignored when synchronous mode is chosen, when the multiprocessor communication function is disabled, or when data transmission is disabled. Bit 0: MPBT 0 1 Description The multiprocessor bit in transmit data is 0 The multiprocessor bit in transmit data is 1 (initial value) Rev.3.00 Jul. 19, 2007 page 273 of 532 REJ09B0397-0300 10. Serial Communication Interface Bit Rate Register (BRR) Bit 7 BRR7 Initial value Read/Write 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W 2 BRR2 1 R/W 1 BRR1 1 R/W 0 BRR0 1 R/W The bit rate register (BRR) is an 8-bit register which, together with the baud rate generator clock selected by bits CKS1 and CKS0 in the serial mode register (SMR), sets the transmit/receive bit rate. BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Table 10.6 gives examples of how BRR is set in asynchronous mode. The values in table 10.6 are for active (high-speed) mode. Table 10.6 BRR Settings and Bit Rates in Asynchronous Mode OSC (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 0 0 0 0 0 0 N 70 207 103 51 25 12 0 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 0 n 1 0 0 0 0 0 0 0 0 0 2.4576 N 86 255 127 63 31 15 7 3 1 0 Error (%) +0.31 0 0 0 0 0 0 0 0 0 n 1 1 0 0 0 0 0 0 N 141 103 207 103 51 25 12 1 4 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 0 n 1 1 0 0 0 0 0 0 4.194304 N 148 108 217 108 54 26 13 6 Error (%) -0.04 +0.21 +0.21 +0.21 -0.70 +1.14 -2.48 -2.48 Rev.3.00 Jul. 19, 2007 page 274 of 532 REJ09B0397-0300 10. Serial Communication Interface OSC (MHz) 4.9152 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 N 174 127 255 127 63 31 15 7 3 1 Error (%) -0.26 0 0 0 0 0 0 0 0 0 n 1 1 1 0 0 0 0 0 0 0 N 212 155 77 155 77 38 19 9 4 2 6 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 -2.34 -2.34 0 n 2 1 1 0 0 0 0 0 0 0 7.3728 N 64 191 95 191 95 47 23 11 5 2 Error (%) +0.70 0 0 0 0 0 0 0 0 0 n 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 3 8 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 0 Rev.3.00 Jul. 19, 2007 page 275 of 532 REJ09B0397-0300 10. Serial Communication Interface OSC (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) +0.31 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 10 Error (%) -0.25 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 +1.73 0 +1.73 Notes: 1. Settings should be made so that error is within 1%. 2. BRR setting values are derived by the following equation. N= OSC x 106 - 1 64 x 22n x B Bit rate (bits/s) BRR baud rate generator setting (0 N 255) Value of OSC (MHz) Baud rate generator input clock number (n = 0 to 3) (The relation between n and the clock is shown in table 10.7.) B: N: OSC: n: 3. The error values in table 10.6 were derived by performing the following calculation and rounding off to two decimal places. Error (%) = B-R x 100 R B: Bit rate found from n, N, and OSC R: Bit rate listed in left column of table 10.6 Rev.3.00 Jul. 19, 2007 page 276 of 532 REJ09B0397-0300 10. Serial Communication Interface The meaning of n is shown in table 10.7. Table 10.7 Relation between n and Clock SMR Setting n 0 1 2 3 Clock /4 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1 Table 10.8 shows the maximum bit rate for selected frequencies in asynchronous mode. Values in table 10.8 are for active (high-speed) mode. Table 10.8 Maximum Bit Rate at Selected Frequencies (Asynchronous Mode) Setting OSC (MHz) 2 2.4576 4 4.194304 4.9152 6 7.3728 8 9.8304 10 Maximum Bit Rate (bits/s) 31250 38400 62500 65536 76800 93750 115200 125000 153600 156250 n 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 Rev.3.00 Jul. 19, 2007 page 277 of 532 REJ09B0397-0300 10. Serial Communication Interface Table 10.9 shows typical BRR settings in synchronous mode. Values in table 10.9 are for active (high-speed) mode. Table 10.9 Typical BRR Settings and Bit Rates (Synchronous Mode) OSC (MHz) Bit Rate (bits/s) 110 250 500 1K 2.5 K 5K 10 K 25 K 50 K 100 K 250 K 500 K 1M 2.5 M Legend: Blank: Cannot be set : Can be set, but error will result *: Continuous transfer not possible at this setting 2 n 1 1 0 0 0 0 0 0 0 N 249 124 249 99 49 24 9 4 0* n 2 1 1 0 0 0 0 0 0 0 0 4 N 124 249 124 199 99 49 19 9 4 1 0* n 2 2 1 1 0 0 0 0 0 0 0 0 8 N 249 124 249 99 199 99 39 19 9 3 1 0* n 1 0 0 0 0 0 10 N 124 249 124 49 24 4 BRR setting values are derived by the following equation. N= OSC x 106 - 1 8 x 22n x B Legend: B: Bit rate (bits/s) N: BRR baud rate generator setting (0 N 255) OSC: Value of OSC (MHz) n: Baud rate generator input clock number (n = 0, 1, 2, 3) Rev.3.00 Jul. 19, 2007 page 278 of 532 REJ09B0397-0300 10. Serial Communication Interface The meaning of n is shown in table 10.10. Table 10.10 Relation between n and Clock SMR Setting n 0 1 2 3 Clock /4 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1 10.3.3 Operation SCI3 supports serial data communication in both asynchronous mode, where each character transferred is synchronized separately, and synchronous mode, where transfer is synchronized by clock pulses. The choice of asynchronous mode or synchronous mode, and the communication format, is made in the serial mode register (SMR), as shown in table 10.11. The SCI3 clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3), as shown in table 10.12. Asynchronous Mode: * Data length: choice of 7 bits or 8 bits * Options include addition of parity bit, multiprocessor bit, and one or two stop bits (transmit/receive format and character length are determined by this combination of options). * Framing error (FER), parity error (PER), overrun error (OER), and line breaks can be detected when data is received. * Clock source: Choice of internal clocks or an external clock When an internal clock is selected: Operates on baud rate generator clock. A clock can be output with the same frequency as the bit rate. When an external clock is selected: A clock input with a frequency 16 times the bit rate is required (internal baud rate generator is not used). Rev.3.00 Jul. 19, 2007 page 279 of 532 REJ09B0397-0300 10. Serial Communication Interface Synchronous Mode: * Transfer format: 8 bits * Overrun error can be detected when data is received. * Clock source: Choice of internal clocks or an external clock When an internal clock is selected: Operates on baud rate generator clock, and outputs a serial clock. When an external clock is selected: The internal baud rate generator is not used. Operation is synchronous with the input clock. Table 10.11 SMR Settings and SCI3 Communication Format SMR Setting Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: COM CHR MP PE STOP Mode 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 * * 1 * * 1 * 0 * 0 1 0 1 * Asynchronous mode 8-bit data Yes No Yes 7-bit data No Asynchronous mode Communication Format MultiproData Length cessor Bit 8-bit data No Parity Bit No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No None (multiprocessor 7-bit data format) Synchronous mode 8-bit data Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 280 of 532 REJ09B0397-0300 10. Serial Communication Interface Table 10.12 SMR and SCR3 Settings and Clock Source Selection SMR Bit 7: COM 0 SCR3 Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 1 Synchronous mode Reserved Mode Asynchronous mode Clock Source Internal Transmit/Receive Clock Pin SCK3 Function I/O port (SCK3 function not used) Outputs clock with same frequency as bit rate External Internal External Clock should be input with frequency 16 times the desired bit rate Outputs a serial clock Inputs a serial clock (illegal settings) Rev.3.00 Jul. 19, 2007 page 281 of 532 REJ09B0397-0300 10. Serial Communication Interface Continuous Transmit/Receive Operation Using Interrupts: Continuous transmit and receive operations are possible with SCI3, using the RXI or TXI interrupts. Table 10.13 explains this use of these interrupts. Table 10.13 Transmit/Receive Interrupts Interrupt RXI Flag RDRF RIE Interrupt Conditions When serial data is received normally and receive data is transferred from RSR to RDR, RDRF is set to 1. If RIE is 1 at this time, RXI is enabled and an interrupt occurs. (See figure 10.4.) When TSR empty (previous transmission complete) is detected and the transmit data set in TDR is transferred to TSR, TDRE is set to 1. If TIE is 1 at this time, TXI is enabled and an interrupt occurs. (See figure 10.5.) Remarks The RXI interrupt handler routine should read the receive data from RDR and clear RDRF to 0. Continuous receiving is possible if these operations are completed before the next data has been completely received in RSR. The TXI interrupt handler routine should write the next transmit data to TDR and clear TDRE to 0.Continuous transmission is possible if these operations are completed before the data transferred to TSR has been completely transmitted. TEI indicates that, when the last bit of the TSR transmit character was sent, the next transmit data had not been written to TDR. TXI TDRE TIE TEI TEND TEIE When the last bit of the TSR transmit character has been sent, if TDRE is 1, then 1 is set in TEND. If TEIE is 1 at this time, TEI is enabled and an interrupt occurs. (See figure 10.6.) RDR RDR RSR (receiving) RXD pin RDRF = 0 RXD pin RSR (received and transferred) RDRF 1 (RXI requested if RIE = 1) Figure 10.4 RDRF Setting and RXI Interrupt Rev.3.00 Jul. 19, 2007 page 282 of 532 REJ09B0397-0300 10. Serial Communication Interface TDR (next transmit data) TDR TSR (transmitting) TXD pin TDRE = 0 TXD pin TSR (transmission complete, next data transferred) TDRE 1 (TXI requested if TIE = 1) Figure 10.5 TDRE Setting and TXI Interrupt TDR TDR TSR (transmitting) TXD pin TEND = 0 TXD pin TSR (transmission end) TEND 1 (TEI requested if TEIE = 1) Figure 10.6 TEND Setting and TEI Interrupt 10.3.4 Operation in Asynchronous Mode In asynchronous communication mode, a start bit indicating the start of communication and a stop bit indicating the end of communication are added to each character that is sent. In this way synchronization is achieved for each character as a self-contained unit. SCI3 consists of independent transmit and receive modules, giving it the capability of full duplex communication. Both the transmit and receive modules have a double-buffer configuration, allowing data to be read or written during communication operations so that data can be transmitted and received continuously. Rev.3.00 Jul. 19, 2007 page 283 of 532 REJ09B0397-0300 10. Serial Communication Interface Transmit/Receive Formats Figure 10.7 shows the general format for asynchronous serial communication. (LSB) Serial data Start bit Transmit or receive data (MSB) Parity bit 1 bit or none Stop bit 1 Mark state 1 bit 7 or 8 bits One unit of data (character or frame) 1 or 2 bits Figure 10.7 Data Format in Asynchronous Serial Communication Mode The communication line in asynchronous communication mode normally stays at the high level, in the "mark" state. SCI3 monitors the communication line, and begins serial data communication when it detects a "space" (low-level signal), which is regarded as a start bit. One character consists of a start bit (low level), transmit/receive data (in LSB-first order: starting with the least significant bit), a parity bit (high or low level), and finally a stop bit (high level), in this order. In asynchronous data receiving, synchronization is with the falling edge of the start bit. SCI3 samples data on the 8th pulse of a clock that has 16 times the frequency of the bit rate, so each bit of data is latched at its center. Table 10.14 shows the 12 transmit/receive formats formats that can be selected in asynchronous mode. The format is selected in the serial mode register (SMR). Rev.3.00 Jul. 19, 2007 page 284 of 532 REJ09B0397-0300 10. Serial Communication Interface Table 10.14 Serial Communication Formats in Asynchronous Mode SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 * * * * MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S S S S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP STOP STOP P STOP P STOP STOP STOP STOP P P STOP STOP STOP MPB STOP MPB STOP STOP MPB STOP MPB STOP STOP Legend: * Don't care S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev.3.00 Jul. 19, 2007 page 285 of 532 REJ09B0397-0300 10. Serial Communication Interface Clock The clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3). See table 10.12 for the settings. Either an internal clock source can be used to run the built-in baud rate generator, or an external clock source can be input at pin SCK3. When an external clock is input at pin SCK3, it should have a frequency 16 times the desired bit rate. When an internal clock source is used, SCK3 is used as the clock output pin. The clock output has the same frequency as the serial bit rate, and is synchronized as in figure 10.8 so that the rising edge of the clock occurs in the center of each bit of transmit/receive data. Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 character (1 frame) Figure 10.8 Phase Relation of Output Clock and Communication Data in Asynchronous Mode (8-Bit Data, Parity Bit Added, and 2 Stop Bits) Data Transmit/Receive Operations SCI3 Initialization: Before data is sent or received, bits TE and RE in serial control register 3 (SCR3) must be cleared to 0, after which initialization can be performed using the procedure shown in figure 10.9. Note: When modifying the operation mode, transfer format or other settings, always be sure to clear bits TE and RE first. When TE is cleared to 0, bit TDRE will be set to 1. Clearing RE does not clear the status flags RDRF, PER, FER, or OER, or alter the contents of the receive data register (RDR). When an external clock is used in asynchronous mode, do not stop the clock during operation, including during initialization. When an external clock is used in synchronous mode, do not supply the clock during initialization. Rev.3.00 Jul. 19, 2007 page 286 of 532 REJ09B0397-0300 10. Serial Communication Interface Figure 10.9 shows a typical flow chart for SCI3 initialization. Start Clear TE and RE to 0 in SCR3 1 Set bits CKE1 and CKE0 2 Select communication format in SMR 3 Set BRR value Wait 1. Select the clock in serial control register 3 (SCR3). Other bits must be cleared to 0. If clock output is selected in asynchronous mode, a clock signal will be output as soon as CKE1 and CKE0 have been set. If clock output is selected for reception in synchronous mode, a clock signal will be output as soon as bits CKE1 and CKE0, and bit RE, are set to 1. 2. Set the transmit/receive format in the serial mode register (SMR). 3. Set the bit rate register (BRR) to the value giving the desired bit rate. This step is not required when an external clock source is used. 4. Wait for at least a 1-bit interval, then set bits RIE, TIE, TEIE, and MPIE, and set bit TE or RE in SCR3 to 1. Setting TE or RE enables SCI3 to use the TXD or RXD pin. The initial states in asynchronous mode are the mark transmit state and the idle receive state (waiting for a start bit). Has a 1-bit interval elapsed? Yes 4 Set bits RIE, TIE, TEIE, and MPIE in SCR3, and set TE or RE to 1 No End Figure 10.9 Typical Flow Chart when SCI3 Is Initialized Rev.3.00 Jul. 19, 2007 page 287 of 532 REJ09B0397-0300 10. Serial Communication Interface Transmitting: Figure 10.10 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start 1 Read bit TDRE in SSR TDRE = 1? Yes Write transmit data in TDR No 1. Read the serial status register (SRR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. 2 Continue data transmission? No Read bit TEND in SSR Yes 2. To continue transmitting data, read bit TDRE to make sure it is set to 1, then write the next data to TDR. When data is written to TDR, TDRE is automatically cleared to 0. No TEND = 1? Yes 3 Break output? Yes Set PDR = 0 and PCR = 1 No 3. To output a break signal when transmission ends, first set the port values PCR = 1 and PDR = 0, then clear bit TE in SCR3 to 0. Clear bit TE in SCR3 to 0 End Figure 10.10 Typical Data Transmission Flow Chart (Asynchronous Mode) Rev.3.00 Jul. 19, 2007 page 288 of 532 REJ09B0397-0300 10. Serial Communication Interface SCI3 operates as follows during data transmission. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is requested. Serial data is transmitted from pin TXD using the communication format outlined in table 10.14. Next, TDRE is checked as the stop bit is being transmitted. If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent the output remains at 1 (mark state). A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1. Figure 10.11 shows a typical operation in asynchronous transmission mode. Start bit Serial data 1 0 D0 Transmit data D1 D7 1 frame TDRE Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 D7 1 frame Parity Stop Mark bit bit state 0/1 1 1 TEND LSI TXI request TDRE cleared to 0 operation User processing Write data in TDR TXI request TEI request Figure 10.11 Typical Transmit Operation in Asynchronous Mode (8-Bit Data, Parity Bit Added, and 1 Stop Bit) Receiving: Figure 10.12 shows a typical flow chart for receiving serial data. After SCI3 initialization, follow the procedure below. Rev.3.00 Jul. 19, 2007 page 289 of 532 REJ09B0397-0300 10. Serial Communication Interface Start 1. Read bits OER, PER, and FER in the serial status register (SSR) to determine if a receive error has occurred. If a receive error has occurred, receive error processing is executed. 2. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read received data from the receive data register (RDR). When RDR data is read, RDRF is automatically cleared to 0. 3. To continue receiving data, read bit RDRF and finish reading RDR before the stop bit of the present frame is received. When data is read from RDR, RDRF is automatically cleared to 0. 4. When a receive error occurs, read bits OER, PER, and FER in SSR to determine which error (s) occurred. After the necessary error processing, be sure to clear the above bits all to 0. Data receiving cannot be resumed while any of bits OER, PER, or FER is set to 1. When a framing error occurs, a break can be detected by reading the RXD pin value. 1 Read bits OER, PER, and FER in SSR OER + PER + FER = 1 No Yes 2 Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR 4 Receive error processing Yes 3 Continue receiving? No A Clear bit RE in SCR3 to 0 End 4 Start receive error processing Yes OER = 1? No Yes FER = 1? No Yes PER = 1? No Clear bits OER, PER, and FER in SSR to 0 End receive error processing Parity error processing Break? No Framing error processing Yes Overrun error processing A Figure 10.12 Typical Serial Data Receiving Flow Chart in Asynchronous Mode Rev.3.00 Jul. 19, 2007 page 290 of 532 REJ09B0397-0300 10. Serial Communication Interface SCI3 operates as follows when receiving serial data in asynchronous mode. SCI3 monitors the communication line, and when a start bit (0) is detected it performs internal synchronization and starts receiving. The communication format for data receiving is as outlined in table 10.14. Received data is set in RSR from LSB to MSB, then the parity bit and stop bit(s) are received. After receiving the data, SCI3 performs the following checks: * Parity check: The number of 1s received is checked to see if it matches the odd or even parity selected in bit PM of SMR. * Stop bit check: The stop bit is checked for a value of 1. If there are two stop bits, only the first bit is checked. * Status check: The RDRF bit is checked for a value of 0 to make sure received data can be transferred from RSR to RDR. If no receive error is detected by the above checks, bit RDRF is set to 1 and the received data is stored in RDR. At that time, if bit RIE in SCR3 is set to 1, an RXI interrupt is requested. If the error check detects a receive error, the appropriate error flag (OER, PER, or FER) is set to 1. RDRF retains the same value as before the data was received. If at this time bit RIE in SCR3 is set to 1, an ERI interrupt is requested. Table 10.15 gives the receive error detection conditions and the processing of received data in each case. Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0. Table 10.15 Receive Error Conditions and Received Data Processing Receive Error Overrun error Framing error Parity error Abbr. OER FER PER Detection Conditions Received Data Processing Receiving of the next data ends while Received data is not bit RDRF in SSR is still set to 1 transferred from RSR to RDR Stop bit is 0 Received data does not match the parity (odd/even) set in SMR Received data is transferred from RSR to RDR Received data is transferred from RSR to RDR Rev.3.00 Jul. 19, 2007 page 291 of 532 REJ09B0397-0300 10. Serial Communication Interface Figure 10.13 shows a typical SCI3 data receive operation in asynchronous mode. Start bit Serial 1 data 0 D0 Receive data D1 D7 1 frame Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark (idle state) 1 RDRF FER LSI operation RXI request RDRF cleared to 0 Read RDR data Detects stop bit = 0 ERI request due to framing error Framing error handling User processing Figure 10.13 Typical Receive Operation in Asynchronous Mode (8-Bit Data, Parity Bit Added, and 1 Stop Bit) 10.3.5 Operation in Synchronous Mode In synchronous mode, data is sent or received in synchronization with clock pulses. This mode is suited to high-speed serial communication. SCI3 consists of independent transmit and receive modules, so full duplex communication is possible, sharing the same clock between both modules. Both the transmit and receive modules have a double-buffer configuration. This allows data to be written during a transmit operation so that data can be transmitted continuously, and enables data to be read during a receive operation so that data can be received continuously. Rev.3.00 Jul. 19, 2007 page 292 of 532 REJ09B0397-0300 10. Serial Communication Interface Transmit/Receive Format Figure 10.14 shows the general communication data format for synchronous communication. * Serial clock LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * 8 bits One unit of communication data (character or frame) Note: * At high level except during continuous transmit/receive. Figure 10.14 Data Format in Synchronous Communication Mode In synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. Data is guaranteed valid at the rising edge of the serial clock. One character of data starts from the LSB and ends with the MSB. The communication line retains the MSB state after the MSB is output. In synchronous receive mode, SCI3 latches receive data in synchronization with the rising edge of the serial clock. The transmit/receive format is fixed at 8-bit data. No parity bit or multiprocessor bit is added in this mode. Clock Either an internal clock from the built-in baud rate generator is used, or an external clock is input at pin SCK3. The choice of clock sources is designated by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3). See table 10.12 for details on selecting the clock source. When operation is based on an internal clock, a serial clock is output at pin SCK3. Eight clock pulses are output per character of transmit/receive data. When no transmit or receive operation is being performed, the pin is held at the high level. Rev.3.00 Jul. 19, 2007 page 293 of 532 REJ09B0397-0300 10. Serial Communication Interface Data Transmit/Receive Operations SCI3 Initialization: Before transmitting or receiving data, follow the SCI3 initialization procedure explained under 10.3.4, SCI3 Initialization, and illustrated in figure 10.9. Transmitting: Figure 10.15 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start 1 Read bit TDRE in SSR No TDRE = 1? Yes Write transmit data in TDR 1. Read the serial status register (SSR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0 and data transmission begins. If clock output has been selected, after data is written to TDR, the clock is output and data transmission begins. Yes 2 Continue data transmission? No 2. To continue transmitting data, read bit TDRE to make sure it is set to 1, then write the next data to TDR. When data is written to TDR, TDRE is automatically cleared to 0. Read bit TEND in SSR TEND = 1? Yes No Write 0 to bit TE in SCR3 End Figure 10.15 Typical Data Transmission Flow Chart in Synchronous Mode Rev.3.00 Jul. 19, 2007 page 294 of 532 REJ09B0397-0300 10. Serial Communication Interface SCI3 operates as follows during data transmission in synchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is requested. If clock output is selected, SCI3 outputs eight serial clock pulses. If an external clock is used, data is output in synchronization with the clock input. Serial data is transmitted from pin TXD in order from LSB (bit 0) to MSB (bit 7). Then TDRE is checked as the MSB (bit 7) is being transmitted. If TDRE is 0, data is transferred from TDR to TSR, and after the MSB (bit 7) is sent, transmission of the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the MSB (bit 7) has been sent, the MSB state is maintained. A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1. After data transmission ends, pin SCK3 is held at the high level. Note: Data transmission cannot take place while any of the receive error flags (OER, FER, PER) is set to 1. Be sure to confirm that these error flags are cleared to 0 before starting transmission. Figure 10.16 shows a typical SCI3 transmit operation in synchronous mode. Serial clock Serial data Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7 TDRE TEND LSI operation User processing TXI request TDRE cleared to 0 Write data in TDR TXI request TEI request Figure 10.16 Typical SCI3 Transmit Operation in Synchronous Mode Rev.3.00 Jul. 19, 2007 page 295 of 532 REJ09B0397-0300 10. Serial Communication Interface Receiving: Figure 10.17 shows a typical flow chart for receiving data. After SCI3 initialization, follow the procedure below. Start 1 Read bit OER in SSR Yes OER = 1? No 1. Read bit OER in the serial status register (SSR) to determine if an error has occurred. If an overrun error has occurred, overrun error processing is executed. 2 Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR 4 Overrun error processing Continue receiving? No Clear bit RE in SCR3 to 0 Yes 2. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read received data from the receive data register (RDR). When data is read from RDR, RDRF is automatically cleared to 0. 3. To continue receiving data, read bit RDRF and read the received data in RDR before the MSB (bit 7) of the present frame is received. When data is read from RDR, RDRF is automatically cleared to 0. 3 End Start overrun processing Overrun error processing Clear bit OER in SSR to 0 End overrun error processing 4. When an overrun error occurs, read bit OER in SSR. After the necessary error processing, be sure to clear OER to 0. Data receiving cannot be resumed while bit OER is set to 1. 4 Figure 10.17 Typical Data Receiving Flow Chart in Synchronous Mode Rev.3.00 Jul. 19, 2007 page 296 of 532 REJ09B0397-0300 10. Serial Communication Interface SCI3 operates as follows when receiving serial data in synchronous mode. SCI3 synchronizes internally with the input or output of the serial clock and starts receiving. Received data is set in RSR from LSB to MSB. After data has been received, SCI3 checks to confirm that the value of bit RDRF is 0 indicating that received data can be transferred from RSR to RDR. If this check passes, RDRF is set to 1 and the received data is stored in RDR. At this time, if bit RIE in SCR3 is set to 1, an RXI interrupt is requested. If an overrun error is detected, OER is set to 1 and RDRF remains set to 1. Then if bit RIE in SCR3 is set to 1, an ERI interrupt is requested. For the overrun error detection conditions and receive data processing, see table 10.15. Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0. Figure 10.18 shows a typical receive operation in synchronous mode. Serial clock Serial data Bit 7 Bit 0 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7 RDRF OER LSI operation User processing RXI request RDRF cleared to 0 Read data from RDR RXI request RDR data not read (RDRF = 1) ERI request due to overrun error Overrun error handling Figure 10.18 Typical Receive Operation in Synchronous Mode Rev.3.00 Jul. 19, 2007 page 297 of 532 REJ09B0397-0300 10. Serial Communication Interface Simultaneous Transmit/Receive: Figure 10.19 shows a typical flow chart for transmitting and receiving simultaneously. After SCI3 synchronization, follow the procedure below. Start 1. Read the serial status register (SSR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. No TDRE = 1? Yes 2 Write transmit data in TDR 2. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read the received data from the receive data register (RDR). When data is read from RDR, RDRF is automatically cleared to 0. 3. To continue transmitting and receiving serial data, read bit RDRF and finish reading RDR before the MSB (bit 7) of the present frame is received. Also read bit TDRE and check that it is set to 1, indicating that data can be written, then write the next data in TDR, before the MSB (bit 7) of the current frame is transmitted. When data is written to TDR, TDRE is automatically cleared to 0; and when data is read from RDR, RDRF is automatically cleared to 0. 4. When an overrun error occurs, read bit OER in SSR. After the necessary error processing, be sure to clear OER to 0. Data transmission and reception cannot take place while bit OER is set to 1. See figure 10.17 for overrun error processing. 1 Read bit TDRE in SSR Read bit OER in SSR Yes OER = 1? No Read RDRF in SSR No RDRF = 1? Yes Read received data in RDR 4 Continue transmitting and receiving? No Clear bits TE and RE in SCR3 to 0 End Overrun error processing Yes 3 Figure 10.19 Simultaneous Transmit/Receive Flow Chart in Synchronous Mode Rev.3.00 Jul. 19, 2007 page 298 of 532 REJ09B0397-0300 10. Serial Communication Interface Notes: 1. To switch from transmitting to simultaneous transmitting and receiving, use the following procedure. * First confirm that TDRE and TEND are both set to 1 and that SCI3 has finished transmitting. Next clear TE to 0. Then set both TE and RE to 1. 2. To switch from receiving to simultaneous transmitting and rceiving, use the following procedure. * After confirming that SCI3 has finished receiving, clear RE to 0. Next, after confirming that RDRF and the error flags (OER FER, PER) are all 0, set both TE and RE to 1. 10.3.6 Multiprocessor Communication Function The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID code. A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The ID-sending cycle and data-sending cycle are differentiated by the multiprocessor bit. The multiprocessor bit is 1 in an ID-sending cycle, and 0 in a data-sending cycle. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. When a receiving processor receives data with the multiprocessor bit set to 1, it compares the data with its own ID. If the data matches its ID, the receiving processor continues to receive incoming data. If the data does not match its ID, the receiving processor skips further incoming data until it again receives data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 10.20 shows an example of communication among different processors using a multiprocessor format. Rev.3.00 Jul. 19, 2007 page 299 of 532 REJ09B0397-0300 10. Serial Communication Interface Transmitting processor Communication line Receiving processor A (ID = 01) Receiving processor B (ID = 02) Receiving processor C (ID = 03) Receiving processor D (ID = 04) Serial data H'01 (MPB = 1) ID-sending cycle (receiving processor address) H'AA (MPB = 0) Data-sending cycle (data sent to receiving processor designated by ID) MPB: Multiprocessor bit Figure 10.20 Example of Interprocessor Communication Using Multiprocessor Format (Data H'AA Sent to Receiving Processor A) Four communication formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 10.14. For a description of the clock used in multiprocessor communication, see section 10.3.4, Operation in Asynchronous Mode. Rev.3.00 Jul. 19, 2007 page 300 of 532 REJ09B0397-0300 10. Serial Communication Interface Transmitting Multiprocessor Data: Figure 10.21 shows a typical flow chart for multiprocessor serial data transmission. After SCI3 initialization, follow the procedure below. Start 1 Read bit TDRE in SSR No Yes Set bit MPBT in SSR TDRE = 1? 1. Read the serial status register (SSR), and after confirming that bit TDRE = 1, set bit MPBT (multiprocessor bit transmit) in SSR to 0 or 1, then write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. Write transmit data to TDR 2 Continue transmitting? No Yes Read bit TEND in SSR 2. To continue transmitting data, read bit TDRE to make sure it is set to 1, then write the next data to TDR. When data is written to TDR, TDRE is automatically cleared to 0. TEND = 1? Yes 3 Break output? Yes Set PDR = 0 and PCR = 1 No No 3. To output a break signal at the end of data transmission, first set the port values PCR = 1 and PDR = 0, then clear bit TE in SCR3 to 0. Clear bit TE in SCR3 to 0 End Figure 10.21 Typical Multiprocessor Data Transmission Flow Chart Rev.3.00 Jul. 19, 2007 page 301 of 532 REJ09B0397-0300 10. Serial Communication Interface SCI3 operates as follows during data transmission using a multiprocessor format. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is requested. Serial data is transmitted from pin TXD using the communication format outlined in table 10.14. Next, TDRE is checked as the stop bit is being transmitted. If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent the output remains at 1 (mark state). A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1. Figure 10.22 shows a typical SCI3 operation in multiprocessor communication mode. Start bit Serial data 1 0 D0 Transmit data D1 D7 MPB 0/1 Stop Start bit bit 1 0 D0 Transmit data D1 D7 MPB 0/1 Stop Mark bit state 1 1 1 frame TDRE TEND 1 frame LSI TXI request operation User processing TDRE cleared to 0 Write data in TDR TXI request TEI request Figure 10.22 Typical Multiprocessor Format Transmit Operation (8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit) Rev.3.00 Jul. 19, 2007 page 302 of 532 REJ09B0397-0300 10. Serial Communication Interface Receiving Multiprocessor Data: Figure 10.23 shows a typical flow chart for receiving data using a multiprocessor format. After SCI3 initialization, follow the procedure below. Start 1 2 Set bit MPIE in SCR3 to 1 Read bits OER and FER in SSR Yes OER + FER = 1? 3 No Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR Own ID? Yes Read bits OER and FER in SSR OER + FER = 1? No 4 Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR 5 Error processing Yes Continue receiving? No Clear bit RE in SCR3 to 0 OER = 1? End No Yes FER = 1? No Clear bits OER and FER in SSR to 0. End receive error processing No Framing error processing A Break? Yes A Start receive error processing Yes Overrun error processing Yes No 5. If a receive error occurs, read bits OER and FER in SSR to determine which error occurred. After the necessary error processing, be sure to clear the error flags to 0. Serial data transfer cannot take place while bit OER or FER is set to 1. When a framing error occurs, a break can be detected by reading the RXD pin value. 1. Set bit MPIE in serial control register 3 (SCR3) to 1. 2. Read bits OER and FER in the serial status register (SSR) to determine if an error has occurred. If a receive error has occurred, receive error processing is executed. 3. Read the serial status register (SSR) and confirm that RDRF = 1. If RDRF = 1, read the data in the received data register (RDR) and compare it with the processor's own ID. If the received data does not match the ID, set bit MPIE to 1 again. Bit RDRF is automatically cleared to 0 when data in the received data register (RDR) is read. 4. Read SSR, check that bit RDRF = 1, then read received data from the receive data register (RDR). Figure 10.23 Typical Flow Chart for Receiving Serial Data Using Multiprocessor Format Rev.3.00 Jul. 19, 2007 page 303 of 532 REJ09B0397-0300 10. Serial Communication Interface Figure 10.24 gives an example of data reception using a multiprocessor format. Start bit Serial data 1 0 D0 Receive data (ID1) D1 D7 Stop Start bit MPB bit 1 1 0 D0 Receive data (data 1) D1 D7 Stop MPB bit 0 1 Mark (idle state) 1 1 frame MPIE RDRF RDR value LSI operation User processing RXI request MPIE cleared to 0 RDRF cleared to 0 Read data from RDR 1 frame ID1 No RXI request RDR state retained If not own ID, set MPIE to 1 again (a) Data does not match own ID Start bit Serial data 1 0 D0 Receive data (ID2) D1 D7 Stop Start MPB bit bit 1 1 0 D0 Receive data (data 2) D1 D7 Stop MPB bit 0 1 Mark (idle state) 1 1 frame MPIE RDRF RDR value LSI operation 1 frame ID1 RXI request MPIE cleared to 0 RDRF cleared to 0 ID2 RXI request RDRF cleared to 0 Data 2 User processing Read data from RDR If own ID, continue receiving Read data from RDR and set MPIE to 1 again (b) Data matches own ID Figure 10.24 Example of Multiprocessor Format Receive Operation (8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit) Rev.3.00 Jul. 19, 2007 page 304 of 532 REJ09B0397-0300 10. Serial Communication Interface 10.3.7 Interrupts SCI3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three receive error interrupts (overrun error, framing error, and parity error). All share a common interrupt vector. Table 10.16 describes each interrupt. Table 10.16 SCI3 Interrupts Interrupt RXI TXI TEI ERI Description Interrupt request due to receive data register full (RDRF) Interrupt request due to transmit data register empty (TDRE) Interrupt request due to transmit end (TEND) Interrupt request due to receive error (OER, FER, or PER) Vector Address H'0024 The interrupt requests are enabled and disabled by bits TIE and RIE of SCR3. When bit TDRE in SSR is set to 1, TXI is requested. When bit TEND in SSR is set to 1, TEI is requested. These two interrupt requests occur during data transmission. The initial value of bit TDRE is 1. Accordingly, if the transmit data empty interrupt request (TXI) is enabled by setting bit TIE to 1 in SCR3 before placing transmit data in TDR, TXI will be requested even though no transmit data has been readied. Likewise, the initial value of bit TEND in SSR is 1. Accordingly, if the transmit end interrupt request (TEI) is enabled by setting bit TEIE to 1 in SCR3 before placing transmit data in TDR, TEI will be requested even though no data has been transmitted. These interrupt features can be used to advantage by programming the interrupt handler to move the transmit data into TDR. When this technique is not used, the interrupt enable bits (TIE and TEIE) should not be set to 1 until after TDR has been loaded with transmit data, to avoid unwanted TXI and TEI interrupts. When bit RDRF in SSR is set to 1, RXI is requested. When any of SSR bits OER, FER, or PER is set to 1, ERI is requested. These two interrupt requests occur during the receiving of data. Details on interrupts are given in section 3.3, Interrupts. Rev.3.00 Jul. 19, 2007 page 305 of 532 REJ09B0397-0300 10. Serial Communication Interface 10.3.8 Application Notes When using SCI3, attention should be paid to the following matters. Relation between Bit TDRE and Writing Data to TDR: Bit TDRE in the serial status register (SSR) is a status flag indicating that TDR does not contain new transmit data. TDRE is automatically cleared to 0 when data is written to TDR. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR regardless of the status of bit TDRE. However, if new data is written to TDR while TDRE is cleared to 0, assuming the data held in TDR has not yet been shifted to TSR, it will be lost. For this reason it is advisable to confirm that bit TDRE is set to 1 before each write to TDR and not write to TDR more than once without checking TDRE in between. Operation when Multiple Receive Errors Occur at the Same Time: When two or more receive errors occur at the same time, the status flags in SSR are set as shown in table 10.17. If an overrun error occurs, data is not transferred from RSR to RDR, and receive data is lost. Table 10.17 SSR Status Flag States and Transfer of Receive Data SSR Status Flags RDRF* OER 1 0 0 1 1 0 1 Note: * 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer (RSR RDR) Receive Error Status Not transferred Transferred Transferred Not transferred Not transferred Transferred Not transferred Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDRF keeps the same state as before the data was received. However, if due to a late read of received data in one frame an overrun error occurs in the next frame, RDRF is cleared to 0 when RDR is read. Break Detection and Processing: Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state SCI3 continues to receive, so if the FER bit is cleared to 0 it will be set to 1 again. Rev.3.00 Jul. 19, 2007 page 306 of 532 REJ09B0397-0300 10. Serial Communication Interface Sending a Mark or Break Signal: When TE is cleared to 0 the TXD pin becomes an I/O port, the level and direction (input or output) of which are determined by the PDR and PCR bits. This feature can be used to place the TXD pin in the mark state or send a break signal. To place the serial communication line in the mark (1) state before TE is set to 1, set the PDR and PCR bits both to 1. Since TE is cleared to 0, TXD becomes a general output port outputting the value 1. To send a break signal during data transmission, set the PCR bit to 1 and clear the PDR bit to 0, then clear TE to 0. When TE is cleared to 0 the transmitter is initialized, regardless of its current state, so the TXD pin becomes an output port outputting the value 0. Receive Error Flags and Transmit Operation (Sysnchronous Mode Only): When a receive error flag (OER, PER, or FER) is set to 1, SCI3 will not start transmitting even if TDRE is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous mode SCI3 operates on a base clock with 16 times the bit rate frequency. In receiving, SCI3 synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure 10.25. 16 clock cycles 8 clock cycles Internal base clock 0 7 15 0 7 15 0 Receive data (RXD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 10.25 Receive Data Sampling Timing in Asynchronous Mode Rev.3.00 Jul. 19, 2007 page 307 of 532 REJ09B0397-0300 10. Serial Communication Interface The receive margin in asynchronous mode can therefore be derived from the following equation. M = {(0.5 - 1/2N) - (D - 0.5) / N - (L - 0.5) F} x 100% ............................ Equation (1) M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0.5 to 1) Frame length (L = 9 to 12) Absolute value of clock frequency error In equation (1), if F (absolute value of clock frequency error) = 0 and D (clock duty cycle) = 0.5, the receive margin is 46.875% as given by equation (2) below. When D = 0.5 and F = 0, M = {0.5 - 1/(2 x 16)} x 100% = 46.875% ................................................ Equation (2) This value is theoretical. In actual system designs a margin of from 20 to 30 percent should be allowed. Relationship between Bit RDRF and Reading RDR: While SCI3 is receiving, it checks the RDRF flag. When a frame of data has been received, if the RDRF flag is cleared to 0, data receiving ends normally. If RDRF is set to 1, an overrun error occurs. RDRF is automatically cleared to 0 when the contents of RDR are read. If RDR is read more than once, the second and later reads will be performed with RDRF cleared to 0. While RDRF is 0, if RDR is read when reception of the next frame is just ending, data from the next frame may be read. This is illustrated in figure 10.26. Rev.3.00 Jul. 19, 2007 page 308 of 532 REJ09B0397-0300 10. Serial Communication Interface Frame 1 Frame 2 Frame 3 Communication line Data 1 Data 2 Data 3 RDRF RDR Data 1 A RDR read B Data 2 RDR read At A , data 1 is read. At B , data 2 is read. Figure 10.26 Relationship between Data and RDR Read Timing To avoid the situation described above, after RDRF is confirmed to be 1, RDR should only be read once and should not be read twice or more. When the same data must be read more than once, the data read the first time should be copied to RAM, for example, and the copied data should be used. An alternative is to read RDR but leave a safe margin of time before reception of the next frame is completed. Specifically, reading of RDR should be completed before bit 7 is transferred in synchronous mode, or before the stop bit is transferred in asynchronous mode. Caution on Switching of SCK3 Function: If pin SCK3 is used as a clock output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock () cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. 1. When an SCK3 function is switched from clock output to non clock-output When stopping data transfer, issue one instruction to clear bits TE and RE in SCR3 to 0 and to set bits CKE1 and CKE0 to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents SCK3 from being used as a general input/output pin. To avoid an intermediate level of voltage from being applied to SCK3, the line connected to SCK3 should be pulled up to the VCC level via a resistor, or supplied with output from an external device. Rev.3.00 Jul. 19, 2007 page 309 of 532 REJ09B0397-0300 10. Serial Communication Interface 2. When an SCK3 function is switched from clock output to general input/output When stopping data transfer, a. Issue one instruction to clear bits TE and RE in SCR3 to 0 and to set bits CKE1 and CKE0 to 1 and 0, respectively. b. Clear bit COM in SMR to 0 c. Clear bits CKE1 and CKE0 in SCR3 to 0 Note that special care is also needed here to avoid an intermediate level of voltage from being applied to SCK3. Caution on Switching TxD Function: If pin TXD is used as a data output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a high level signal for one system clock () cycle immediately after it is switched. Rev.3.00 Jul. 19, 2007 page 310 of 532 REJ09B0397-0300 11. 14-Bit PWM (H8/3857 Group Only) Section 11 14-Bit PWM (H8/3857 Group Only) 11.1 Overview The H8/3857 Group is provided with a 14-bit PWM (pulse width modulator), which can be used as a D/A converter by connecting a low-pass filter. The H8/3854 Group does not have this module. 11.1.1 Features Features of the 14-bit PWM are as follows. * Choice of two conversion periods A conversion period of 32,768/, with a minimum modulation width of 2/ (PWCR0 = 1), or a conversion period of 16,384/, with a minimum modulation width of 1/ (PWCR0 = 0), can be chosen. * Pulse division method for less ripple 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the 14-bit PWM. PWDRL /2 /4 PWM waveform generator PWCR PWM Legend: PWDRL: PWM data register L PWDRU: PWM data register U PWCR: PWM control register Figure 11.1 Block Diagram of the 14 bit PWM Rev.3.00 Jul. 19, 2007 page 311 of 532 REJ09B0397-0300 Internal data bus PWDRU 11. 14-Bit PWM (H8/3857 Group Only) 11.1.3 Pin Configuration Table 11.1 shows the output pin assigned to the 14-bit PWM. Table 11.1 Pin Configuration Name PWM output pin Abbr. PWM I/O Output Function Pulse-division PWM waveform output 11.1.4 Register Configuration Table 11.2 shows the register configuration of the 14-bit PWM. Table 11.2 Register Configuration Name PWM control register PWM data register U PWM data register L Abbr. PWCR PWDRU PWDRL R/W W W W Initial Value H'FE H'C0 H'00 Address H'FFD0 H'FFD1 H'FFD2 11.2 11.2.1 Bit Register Descriptions PWM Control Register (PWCR) 7 6 1 5 1 4 1 3 1 2 1 1 1 0 PWCR0 0 W Initial value Read/Write 1 PWCR is an 8-bit write-only register for input clock selection. Upon reset, PWCR is initialized to H'FE. Bits 7 to 1--Reserved Bits: Bits 7 to 1 are reserved; they are always read as 1, and cannot be modified. Rev.3.00 Jul. 19, 2007 page 312 of 532 REJ09B0397-0300 11. 14-Bit PWM (H8/3857 Group Only) Bit 0--Clock Select 0 (PWCR0): Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a write-only bit; it is always read as 1. Bit 0: PWCR0 0 1 Description The input clock is /2 (t = 2/). The conversion period is 16,384/, with a minimum modulation width of 1/. (initial value) The input clock is /4 (t = 4/). The conversion period is 32,768/, with a minimum modulation width of 2/. Note: t: Period of PWM input clock 11.2.2 Bit PWDRU PWM Data Registers U and L (PWDRU, PWDRL) 7 1 7 6 1 6 5 4 3 2 1 0 PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 Initial value Read/Write Bit PWDRL Initial value Read/Write PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle. When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM waveform generator, updating the PWM waveform generation data. The 14-bit data should always be written in the following sequence, first to PWDRL and then to PWDRU. 1. Write the lower 8 bits to PWDRL. 2. Write the upper 6 bits to PWDRU. PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1. Upon reset, PWDRU and PWDRL are initialized to H'C000. Rev.3.00 Jul. 19, 2007 page 313 of 532 REJ09B0397-0300 11. 14-Bit PWM (H8/3857 Group Only) 11.3 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P14/PWM is designated for PWM output. 2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32,768/ (PWCR0 = 1) or 16,384/ (PWCR0 = 0). 3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data in these registers will be latched in the PWM waveform generator, updating the PWM waveform generation in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 11.2. The total of the highlevel pulse widths during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be represented as follows. TH = (data value in PWDRU and PWDRL + 64) x t /2 where t is the PWM input clock period, either 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1). Example: Settings in order to obtain a conversion period of 8,192 s: When bit PWCR0 = 0, the conversion period is 16,384/, so must be 2 MHz. In this case tfn = 128 s, with 1/ (resolution) = 0.5 s. When bit PWCR0 = 1, the conversion period is 32,768/, so must be 4 MHz. In this case tfn = 128 s, with 2/ (resolution) = 0.5 s. Accordingly, for a conversion period of 8,192 s, the system clock frequency () must be 2 MHz or 4 MHz. 1 conversion period t f1 t f2 t f63 t f64 t H1 t H2 t H3 t H63 t H64 TH = t H1 + t H2 + t H3 + ..... t H64 t f1 = t f2 = t f3 ..... = t f64 Figure 11.2 PWM Output Waveform Rev.3.00 Jul. 19, 2007 page 314 of 532 REJ09B0397-0300 12. A/D Converter Section 12 A/D Converter 12.1 Overview The H8/3857 Group and H8/3854 Group include a resistance-ladder-based successiveapproximation analog-to-digital converter. The maximum number of analog input channels is eight in the H8/3857 Group and four in the H8/3854 Group. 12.1.1 Features The A/D converter has the following features. * 8-bit resolution * Input channels 8 in H8/3857 Group 4 in H8/3854 Group * Conversion time: approx. 12.4 s per channel (at 5 MHz operation) * Built-in sample-and-hold function * Interrupt requested on completion of A/D conversion * A/D conversion can be started by external trigger input Rev.3.00 Jul. 19, 2007 page 315 of 532 REJ09B0397-0300 12. A/D Converter 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ADTRG A/D mode register AVCC*2 + Comparator - Reference voltage AVSS*2 A/D result register Control logic AVCC*2 AVSS*2 Notes: 1. AN0 to AN3 are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group. 2. AVCC and AVSS are functions of the H8/3857 Group only. In the H8/3854 Group, AVCC = VCC and AVSS = VSS. Figure 12.1 Block Diagram of the A/D Converter Rev.3.00 Jul. 19, 2007 page 316 of 532 REJ09B0397-0300 Internal data bus IRRAD AN0*1 AN1*1 AN2*1 AN3*1 AN4 AN5 AN6 AN7 Multiplexer A/D start register 12. A/D Converter 12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbr. I/O Input Input Input Input Input Input Input Input Input Input Input Function Power supply and reference voltage of analog part Ground and reference voltage of analog part Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 External trigger input for starting A/D conversion Analog power supply pin* AVCC Analog ground pin* Analog input pin 0* Analog input pin 1* Analog input pin 2* Analog input pin 3* Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 External trigger input pin Note: * AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG The analog power supply pin, analog ground pin, and analog input pins 0 to 3 are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group. In the H8/3854 Group, the analog power supply pin is the power supply pin (VCC), and the analog ground pin is the ground pin (VSS). 12.1.4 Register Configuration Table 12.2 shows the A/D converter register configuration. Table 12.2 Register Configuration Name A/D mode register A/D start register A/D result register Abbr. AMR ADSR ADRR R/W R/W R/W R Initial Value H'30 H'7F Undefined Address H'FFC4 H'FFC6 H'FFC5 Rev.3.00 Jul. 19, 2007 page 317 of 532 REJ09B0397-0300 12. A/D Converter 12.2 12.2.1 Bit Register Descriptions A/D Result Register (ADRR) 7 ADR7 6 ADR6 R 5 ADR5 R 4 ADR4 R 3 ADR3 R 2 ADR2 R 1 ADR1 R 0 ADR0 R Initial value Read/Write Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-todigital conversion. ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data is held in ADRR until the next conversion operation starts. ADRR is not cleared on reset. 12.2.2 Bit A/D Mode Register (AMR) 7 CKS 6 TRGE 0 R/W 5 1 4 1 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value Read/Write 0 R/W AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger option, and the analog input pins. Upon reset, AMR is initialized to H'30. Bit 7--Clock Select (CKS): Bit 7 sets the A/D conversion speed. Conversion Time Bit 7: CKS 0 1 Note: * Conversion Period 62/ (initial value) 31/ = 2 MHz 31 s 15.5 s = 5 MHz 12.4 s * Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a value of at least 12.4 s. Rev.3.00 Jul. 19, 2007 page 318 of 532 REJ09B0397-0300 12. A/D Converter Bit 6--External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6: TRGE 0 1 Note: * Description Disables start of A/D conversion by external trigger (initial value) Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* The external trigger (ADTRG) edge is selected by bit INTEG4 of the IRQ edge select register (IEGR). See Interrupt Edge Select Register (IEGR) in section 3.3.2, Interrupt Control Registers, for details. Bits 5 and 4--Reserved Bits: Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. Bits 3 to 0--Channel Select (CH3 to CH0): Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3: CH3 0 Bit 2: CH2 0 1 Bit 1: CH1 * 0 Bit 0: CH0 * 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 * * Analog Input Channel No channel selected AN0* 1 (initial value) AN1*1 AN2*1 AN3*1 AN4 AN5 AN6 AN7 Reserved Legend: * Don't care Note: 1. Channels AN0 to AN3 are functions of the H8/3857 Group only, and must not be selected in the H8/3854 Group. Rev.3.00 Jul. 19, 2007 page 319 of 532 REJ09B0397-0300 12. A/D Converter 12.2.3 Bit A/D Start Register (ADSR) 7 ADSF 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value Read/Write 0 R/W The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the converted data is set in the A/D result register (ADRR), and at the same time ADSF is cleared to 0. Bit 7--A/D Start Flag (ADSF): Bit 7 controls and indicates the start and end of A/D conversion. Bit 7: ADSF 0 Description Read: Indicates the completion of A/D conversion Write: Stops A/D conversion 1 Read: Indicates A/D conversion in progress Write: Starts A/D conversion (initial value) Bits 6 to 0--Reserved Bits: Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. Rev.3.00 Jul. 19, 2007 page 320 of 532 REJ09B0397-0300 12. A/D Converter 12.3 12.3.1 Operation A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is set to 1. If the conversion time or input channel needs to be changed in the A/D mode register (AMR) during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 Start of A/D Conversion by External Trigger Input The A/D converter can be made to start A/D conversion by input of an external trigger signal. External trigger input is enabled at pin ADTRG when bit IRQ4 in port mode register 2 (PMR2) is set to 1, and bit TRGE in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of the IRQ edge select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion. Figure 12.2 shows the timing. Pin ADTRG (when bit IEG4 = 0) ADSF A/D conversion Figure 12.2 External Trigger Input Timing Rev.3.00 Jul. 19, 2007 page 321 of 532 REJ09B0397-0300 12. A/D Converter 12.4 Interrupts When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2). For further details see section 3.3, Interrupts. 12.5 Typical Use An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 12.3 shows the operation timing. * Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. * When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is stored in the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D converter goes to the idle state. * Bit IENAD = 1, so an A/D conversion end interrupt is requested. * The A/D interrupt handling routine starts. * The A/D conversion result is read and processed. * The A/D interrupt handling routine ends. If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter. Rev.3.00 Jul. 19, 2007 page 322 of 532 REJ09B0397-0300 Interrupt (IRRAD) Set * IENAD ADSF A/D conversion starts Set * Set * Channel 1 (AN1) operation state Idle A/D conversion (1) Idle A/D conversion (2) Idle Read conversion result A/D conversion result (1) Read conversion result A/D conversion result (2) ADRR Figure 12.3 Typical A/D Converter Operation Timing Note: * ( ) indicates instruction execution by software. 12. A/D Converter Rev.3.00 Jul. 19, 2007 page 323 of 532 REJ09B0397-0300 12. A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRR data Yes Perform A/D conversion? No End Figure 12.4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software) Rev.3.00 Jul. 19, 2007 page 324 of 532 REJ09B0397-0300 12. A/D Converter Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? No Yes Clear bit IRRAD to 0 in IRR2 Read ADRR data Yes Perform A/D conversion? No End Figure 12.5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used) 12.6 Application Notes * Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. * Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. Rev.3.00 Jul. 19, 2007 page 325 of 532 REJ09B0397-0300 12. A/D Converter Rev.3.00 Jul. 19, 2007 page 326 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Section 13 Dot Matrix LCD Controller (H8/3857 Group) 13.1 Overview The LCD controller has built-in display RAM, and performs dot matrix LCD display. One bit of display RAM data corresponds to illumination or non-illumination of one dot on the LCD panel, making possible displays with an extremely high degree of freedom. The LCD controller incorporates all the functions required for LCD display, allowing a dot matrix display of up to 40 x 32 dots. I/O ports are used for the interface with the CPU, offering excellent software heritability when using a combination of MPU and LCD driver. This module operates on the subclock, making it ideal for use in small portable devices. 13.1.1 Features * Built-in bit-mapped display RAM (2084 bits) Maximum of 1280 display bits (selectable from 40 x 32 bits, 56 x 16 bits, 64 x 8 bits, 40 x 16 bits, or 40 x 8 bits) * Choice of 1/8, 1/16, or 1/32 duty * Low power consumption enabling extended drive on battery power Subclock operation Module standby * Built-in 2X or 3X LCD power supply step-up circuit * Comprehensive display control functions Display data read/write, display on/off control, vertical display scrolling, arbitrary area blinking, read-modify-write * CPU interface I/O port interface * Built-in contrast control circuit * Built-in LCD power supply bleeder resistances and voltage follower type op-amp circuits Rev.3.00 Jul. 19, 2007 page 327 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the LCD controller. COM17/ COM32/ SEG56 SEG41 SEG40 COM16/ COM9/ SEG1 SEG57 SEG64 COM8 COM1 Common/segment driver Segment driver Common/segment driver Common driver Level shifter MPX MPX MPX MPX Decoder Common counter Blink control Blink counter Blink start line register Latch 2 Latch 1 Comparator Blink end line register Display line counter Y decoder 64 x 32-bit display memory M P X Display start line register X decoder Display data register Address register Control register 1/2 Blink register Index register Contrast control register Frame frequency setting register LCD drive level power supply selection circuit LCD drive step-up circuit CPU interface V1OUT V2OUT V4OUT V5OUT V3OUT V3 V34 VLCD V4 VLOUT Vci C1+ C2+ C1- C2- RS R/W DB7 DB6 STRB DB4 DB3 DB5 DB1 DB0 DB2 Chip-internal I/O port interface Figure 13.1 Block Diagram of LCD Controller Rev.3.00 Jul. 19, 2007 page 328 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.1.3 Pin Configuration Table 13.1 shows the pins assigned to the LCD controller. Table 13.1 Pin Configuration Pin Name Common output pins Segment output pins LCD bias setting pins LCD test pin LCD step-up capacitance connection pins LCD drive power supply level LCD step-up circuit reference power supply Abbr. COM1 to COM32 SEG1 to SEG64 V3, V4 V34 C1+, C1- C2+, C2- I/O Function Output LCD common drive pins Output LCD segment drive pins Input Input LCD bias setting Internal resistance test pins, shorted to V3 For connection of external capacitances for LCD step-up LCD drive power supply level input/output pins Reference input voltage for LCD step-up circuit, also functioning as step-up circuit power supply V1OUT to V5OUT I/O VCi Input LCD step-up power supply VLOUT output pin LCD drive power supply VLCD Output LCD step-up voltage output pin Input LCD drive power supply input pin Rev.3.00 Jul. 19, 2007 page 329 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.1.4 Register Configuration The LCD controller has one index register and ten control registers, all of which are accessed via an I/O port interface. Except for the display data register (LR4), these registers cannot be read. The LCD controller register configuration is shown in table 13.2. Table 13.2 Register Configuration Index Register Name Index register Control register 1 Control register 2 Address register Frame frequency setting register Display data register Display start line register Blink register Blink start line register Blink end line register Contrast control register Abbr. IR LR0 LR1 LR2 LR3 LR4 LR5 LR6 LR8 LR9 LRA R/W W W W W W R/W W W W W W 1 1 0 1 0 1 0 1 RS 0 1 IR3 0 IR2 0 IR1 0 IR0 0 1 0 1 0 1 0 0 1 0 13.2 13.2.1 Bit Register Descriptions Index Register (IR) 7 6 5 4 3 IR3 0 W 2 IR2 0 W 1 IR1 0 W 0 IR0 0 W Initial value Read/Write IR is an 8-bit write-only register that selects one of the LCD controller's ten control registers. IR is selected when RS is 0. Upon reset, IR is initialized to H'00. Bits 7 to 4--Reserved Bits: Bits 7 to 4 are reserved; they should always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 330 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Bits 3 to 0--Index Register (IR3 to IR0): Bits 3 to 0 are used to select one of the LCD controller's ten control registers. The correspondence between the settings of IR3 to IR0 and the selected registers is shown in table 13.2. Other settings are invalid. 13.2.2 Bit Control Register 1 (LR0) 7 6 5 LSBY 0 W 4 PWR 0 W 3 2 SOB 0 W 1 DDTY1 0 W 0 DDTY0 0 W Initial value Read/Write LR0 is an 8-bit write-only register that performs LCD module standby mode setting, step-up circuit control, switching between character display and graphic display, and drive duty selection. Upon reset, LR0 is initialized to H'00. Bits 7 and 6--Reserved Bits: Bits 7 and 6 are reserved; they should always be cleared to 0. Bit 5--Module Standby (LSBY): Bit 5 is the module standby setting bit. When LSBY is set to 1, the LCD controller enters standby mode. At this time, the state of the PWR bit is not affected, but the DISP and OPON bits in LR1 are reset. Bit 5: LSBY Description 0 1 LCD controller operates normally (initial value) Step-up and internal operations halt, display is turned off, and LCD controller enters standby mode Bit 4--Step-Up Circuit Operation Setting (PWR): Bit 4 selects operation or halting of the stepup circuit. Bit 4: PWR 0 1 Description Step-up circuit halts Step-up circuit operates (initial value) Bit 3--Reserved Bit: Bit 3 is reserved; it should always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 331 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Bit 2--Display Mode Select (SOB): Bit 2 selects either character display mode or graphic display mode. Bit 2: SOB 0 Description Character display mode Bits 4 to 0 of one display memory data byte are output to the segment pins (initial value) 1 Graphic display mode All bits in one display memory data byte are output to the segment pins The X address that can be output is in the range H'0 to H'4 in the case of 1/32 duty, H'0 to H'6 in the case of 1/16 duty, and H'0 to H'7 in the case of 1/8 duty Bits 1 and 0--Display Duty Select (DDTY1, DDTY0): Bits 1 and 0 select a display duty of 1/32, 1/16, or 1/8. Bit 1: DDTY1 Bit 0: DDTY0 Description 0 0 1 1 * 1/32 duty selected 1/16 duty selected Y address H'10 to H'1F display data is invalid 1/8 duty selected Y address H'8 to H'1F display data is invalid Legend: * Don't care (initial value) Rev.3.00 Jul. 19, 2007 page 332 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.3 Bit Control Register 2 (LR1) 7 6 DISP 0 W 5 4 OPON 0 W 3 RMW 0 W 2 1 INC 0 W 0 BLK 0 W Initial value Read/Write LR1 is an 8-bit write-only register that selects operation or halting of LCD display and the op-amp circuits, performs read-modify-write mode setting, and selects the address to be incremented in the display memory. Upon reset, LR1 is initialized to H'00. Bit 7--Reserved Bit: Bit 7 is reserved; it should always be cleared to 0. Bit 6--LCD Operation Setting (DISP): Bit 6 selects operation or halting of the LCD display. When the LSBY bit in LR0 is set to 1, DISP is cleared. Bit 6: DISP 0 1 Description LCD is turned off. All LCD outputs go to the VSS level LCD is turned on (initial value) Bit 5--Reserved Bit: Bit 5 is reserved; it should always be cleared to 0. Bit 4--Op-Amp Circuit Operation Setting (OPON): Bit 4 selects operation or halting of the opamp circuits. When the LCD drive power supply level is applied to V1OUT to V5OUT from an external source, OPON must be cleared to 0. When the LSBY bit in LR0 is set to 1, OPON is cleared. Bit 4: OPON Description 0 1 Built-in op-amps are halted, and output becomes high-impedance. LCD drive voltage can be input from external source (initial value) Built-in op-amps operate Rev.3.00 Jul. 19, 2007 page 333 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Bit 3--Read-Modify-Write Setting (RMW): Bit 3 selects whether display memory X or Y address incrementing is carried out after a write/read access, or only after a write access (readmodify-write mode). Bit 3: RMW 0 1 Description Address is incremented after write/read access to display memory Read-modify-write mode is set In this mode, address is incremented only after write access to display memory (initial value) Bit 2--Reserved Bit: Bit 2 is reserved; it should always be cleared to 0. Bit 1--Increment Address Select (INC): Bit 1 selects either the X address or the Y address as the address to be incremented after the display memory access specified by the RMW bit. The selected address is cleared after a display memory access with the maximum value for the valid display data area; in this case the other address is incremented. Bit 1: INC 0 1 Description Incrementing of display memory Y address has priority; X address is incremented after Y address overflow (initial value) Incrementing of display memory X address has priority; Y address is incremented after X address overflow Bit 0--Blink Operation Setting (BLK): Bit 0 enables or disables the blink function. If BLK is set to 1 while the DISP bit is set to 1 and LCD display is operating, the blink function is enabled and blinking operates in the range set by BK7 to BK0 in LR6, BSL4 to BSL0 in LR8, and BEL4 to BEL0 in LR9. Bit 0: BLK 0 1 Description Blinking is disabled Blinking is enabled (initial value) Rev.3.00 Jul. 19, 2007 page 334 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.4 Bit Address Register (LR2) 7 XA2 6 XA1 0 W 5 XA0 0 W 4 YA4 0 W 3 YA3 0 W 2 YA2 0 W 1 YA1 0 W 0 YA0 0 W Initial value Read/Write 0 W LR2 is an 8-bit write-only register that sets the display memory X- and Y-direction addresses accessed by the CPU. Upon reset, LR2 is initialized to H'00. Bits 7 to 5--X Address Setting (XA2 to XA0): Bits 7 to 5 set the display memory X-direction address. A value from H'0 to H'7 can be set, but if the SOB bit in LR0 is set to 1, display data H'7 is invalid with 1/16 duty, and display data from H'5 to H'7 is invalid with 1/32 duty. When the INC bit in LR1 is set to 1, the address is automatically incremented after the access specified by the RMW bit in LR1, and is cleared after an access with the maximum value for the valid display data area. When INC is 0 and YA4 to YA0 represent the maximum value for the valid display data area, the address is incremented after the access specified by RMW. Bits 4 to 0--Y Address Setting (YA4 to YA0): Bits 4 to 0 set the display memory Y-direction address. A value from H'00 to H'1F can be set, but display data from H'10 to H'1F is invalid with 1/16 duty, and display data from H'08 to H'1F is invalid with 1/8 duty. When the INC bit in LR1 is cleared to 0, the address is automatically incremented after the access specified by the RMW bit in LR1, and is cleared after an access with the maximum value for the valid display data area. When INC is 1 and XA2 to XA0 represent the maximum value for the valid display data area, the address is incremented after the access specified by RMW. Rev.3.00 Jul. 19, 2007 page 335 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.5 Bit Frame Frequency Setting Register (LR3) 7 6 5 FS5 0 W 4 FS4 0 W 3 FS3 0 W 2 FS2 0 W 1 FS1 0 W 0 FS0 0 W Initial value Read/Write LR3 is an 8-bit write-only register that sets the frame frequency. Upon reset, LR3 is initialized to H'00. Bits 7 and 6--Reserved Bits: Bits 7 and 6 are reserved; they should always be cleared to 0. Bits 5 to 0--Frame Frequency Setting (FS5 to FS0): Bits 5 to 0 control the subclock division ratio and set the LCD frame frequency. The relationship between the LCD frame frequency fF (Hz), the subclock frequency fW (Hz), the division ratio r, and the LCD duty 1/N is as follows: fF = fW rxN Set a division ratio suitable for the characteristics of the LCD panel used. The correspondence between register settings and division ratios is shown in table 13.3. Rev.3.00 Jul. 19, 2007 page 336 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Table 13.3 Register Settings and Division Ratios FS FS FS FS Division Division Division Division 5 4 3 2 1 0 Ratio r 5 4 3 2 1 0 Ratio r 5 4 3 2 1 0 Ratio r 5 4 3 2 1 0 Ratio r 0000002 0000014 0000106 0000118 0 0 0 1 0 0 10 0 0 0 1 0 1 12 0 0 0 1 1 0 14 0 0 0 1 1 1 16 0 0 1 0 0 0 18 0 0 1 0 0 1 20 0 0 1 0 1 0 22 0 0 1 0 1 1 24 0 0 1 1 0 0 26 0 0 1 1 0 1 28 0 0 1 1 1 0 30 0 0 1 1 1 1 32 0 1 0 0 0 0 34 0 1 0 0 0 1 36 0 1 0 0 1 0 38 0 1 0 0 1 1 40 0 1 0 1 0 0 42 0 1 0 1 0 1 44 0 1 0 1 1 0 46 0 1 0 1 1 1 48 0 1 1 0 0 0 50 0 1 1 0 0 1 52 0 1 1 0 1 0 54 0 1 1 0 1 1 56 0 1 1 1 0 0 58 0 1 1 1 0 1 60 0 1 1 1 1 0 62 0 1 1 1 1 1 64 1 0 0 0 0 0 66 1 0 0 0 0 1 68 1 0 0 0 1 0 70 1 0 0 0 1 1 72 1 0 0 1 0 0 74 1 0 0 1 0 1 76 1 0 0 1 1 0 78 1 0 0 1 1 1 80 1 0 1 0 0 0 82 1 0 1 0 0 1 84 1 0 1 0 1 0 86 1 0 1 0 1 1 88 1 0 1 1 0 0 90 1 0 1 1 0 1 92 1 0 1 1 1 0 94 1 0 1 1 1 1 96 1 1 0 0 0 0 98 1 1 0 0 0 1 100 1 1 0 0 1 0 102 1 1 0 0 1 1 104 1 1 0 1 0 0 106 1 1 0 1 0 1 108 1 1 0 1 1 0 110 1 1 0 1 1 1 112 1 1 1 0 0 0 114 1 1 1 0 0 1 116 1 1 1 0 1 0 118 1 1 1 0 1 1 120 1 1 1 1 0 0 122 1 1 1 1 0 1 124 1 1 1 1 1 0 126 1 1 1 1 1 1 128 Examples of subclock frequency, LCD duty, and division ratio settings, and frame frequencies, are shown in table 13.4. Table 13.4 Sample Frame Frequency Settings Subclock Frequency (kHz) Display Duty 1/N 1/8 Division ratio r Frame frequency fF (Hz) 1/16 Division ratio r Frame frequency fF (Hz) 1/32 Division ratio r Frame frequency fF (Hz) 32.768 48 85.3 24 85.3 12 85.3 38.4 56 85.7 28 85.7 14 85.7 Rev.3.00 Jul. 19, 2007 page 337 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.6 Bit Display Data Register (LR4) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Initial value Read/Write Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W LR4 is an 8-bit read/write register used to perform read/write access to the display memory specified by XA2 to XA0 and YA4 to YA0 in LR2. In a write to display memory, the write is performed directly to the display memory via this register. In a read, the data is temporarily latched into this register before being output to the bus. After a reset, the display memory and LR4 contents are undefined. 13.2.7 Bit Display Start Line Register (LR5) 7 6 5 4 ST4 0 W 3 ST3 0 W 2 ST2 0 W 1 ST1 0 W 0 ST0 0 W Initial value Read/Write LR5 is an 8-bit write-only register that specifies the line at which display starts. Upon reset, LR5 is initialized to H'00. Bits 7 to 5--Reserved Bits: Bits 7 to 5 are reserved; they should always be cleared to 0. Bits 4 to 0--Display Start Line Setting (ST4 to ST0): Bits 4 to 0 specify the line at which display starts. Set a value of [display start line - 1]. Changing the setting in this register enables vertical scrolling to be implemented. The possible settings are 0 to 31 for 1/32 duty, 0 to 15 for 1/16 duty, and 0 to 7 for 1/8 duty. Display will not be performed normally if these ranges are exceeded. Rev.3.00 Jul. 19, 2007 page 338 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.8 Bit Blink Register (LR6) 7 BK7 6 BK6 0 W 5 BK5 0 W 4 BK4 0 W 3 BK3 0 W 2 BK2 0 W 1 BK1 0 W 0 BK0 0 W Initial value Read/Write 0 W LR6 is an 8-bit write-only register that specifies blink areas. An area is made to blink by writing 1 to the corresponding bit in this register. There are no restrictions on areas that can blink simultaneously, and the entire screen can be made to blink by writing 1 to all the bits. The setting in this register is valid only when the BLK bit in LR1 is set to 1. The blink areas corresponding to the register bits depend on the value of the SOB bit in LR0, as shown below. SOB 0 1 BK7 BK6 BK5 BK4 BK3 BK2 BK1 BK0 SEG1 to SEG5 SEG1 to SEG8 SEG36 to SEG31 to SEG26 to SEG21 to SEG16 to SEG11 to SEG6 to SEG40 SEG35 SEG30 SEG25 SEG20 SEG15 SEG10 SEG57 to SEG49 to SEG41 to SEG33 to SEG25 to SEG17 to SEG9 to SEG64 SEG56 SEG48 SEG40 SEG32 SEG24 SEG16 Upon reset, LR6 is initialized to H'00. 13.2.9 Bit Blink Start Line Register (LR8) 7 6 5 4 BSL4 0 W 3 BSL3 0 W 2 BSL2 0 W 1 BSL1 0 W 0 BSL0 0 W Initial value Read/Write LR8 is an 8-bit write-only register that specifies the start line of an area made to blink. Upon reset, LR8 is initialized to H'00. Bits 7 to 5--Reserved Bits: Bits 7 to 5 are reserved; they should always be cleared to 0. Bits 4 to 0--Blink Start Line Setting (BSL4 to BSL0): Bits 4 to 0 specify the start line of an area made to blink. Set a value of [blink start line - 1]. Rev.3.00 Jul. 19, 2007 page 339 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) The possible settings are 0 to 31 for 1/32 duty, 0 to 15 for 1/16 duty, and 0 to 7 for 1/8 duty. Normal operation is not guaranteed if these ranges are exceeded. 13.2.10 Blink End Line Register (LR9) Bit 7 Initial value Read/Write 6 5 4 BEL4 0 W 3 BEL3 0 W 2 BEL2 0 W 1 BEL1 0 W 0 BEL0 0 W LR9 is an 8-bit write-only register that specifies the end line of an area made to blink. Upon reset, LR9 is initialized to H'00. Bits 7 to 5--Reserved Bits: Bits 7 to 5 are reserved; they should always be cleared to 0. Bits 4 to 0--Blink End Line Setting (BEL4 to BEL0): Bits 4 to 0 specify the end line of an area made to blink. Set a value of [blink end line - 1]. The possible settings are 0 to 31 for 1/32 duty, 0 to 15 for 1/16 duty, and 0 to 7 for 1/8 duty. Normal operation is not guaranteed if these ranges are exceeded. 13.2.11 Contrast Control Register (LRA) Bit 7 Initial value Read/Write 6 5 4 3 CCR3 0 W 2 CCR2 0 W 1 CCR1 0 W 0 CCR0 0 W LRA is an 8-bit write-only register that specifies the contrast control resistance value. Upon reset, LRA is initialized to H'00. Bits 7 to 4--Reserved Bits: Bits 7 to 4 are reserved; they should always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 340 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Bits 3 to 0--Contrast Control Setting (CCR3 to CCR0): Bits 3 to 0 specify the value of the contrast control resistance between the VLCD and V1 levels. By adjusting the contrast control resistance between the VLCD and V1 levels, it is possible to adjust the contrast of the LCD panel. The contrast control resistance can be set in the range from 0.1R to 1.6R, where R is the LCD bleeder resistance. Bit 3: CCR3 0 Bit 2: CCR2 0 Bit 1: CCR1 0 Bit 0: CCR0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Contrast Control Resistance 1.6R 1.5R 1.4R 1.3R 1.2R 1.1R 1.0R 0.9R 0.8R 0.7R 0.6R 0.5R 0.4R 0.3R 0.2R 0.1R (initial value) Rev.3.00 Jul. 19, 2007 page 341 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3 13.3.1 Operation System Overview The LCD controller operates at 1/32, 1/16, or 1/8 duty. The display size is a maximum of 40 x 32 dots (4 rows of 8 columns with a 5 x 8-dot font). As the LCD controller operates on the subclock to perform display control, the time, etc., can be constantly displayed. As this module includes a built-in 2X or 3X LCD power supply step-up circuit, an LCD system can be configured with just a few external parts (resistors and capacitors). Also, since data in the display RAM is retained even in module standby mode, and step-up operation is not performed, low power consumption can be achieved without affecting the display. H8/3857 RS R/W CPU STRB DB7 to DB0 COM1 to COM32 LCD panel LCD controller SEG1 to SEG64 Figure 13.2 System Block Diagram Rev.3.00 Jul. 19, 2007 page 342 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.2 CPU Interface The LCD controller's registers are not included in the memory map shown in figure 2.16 (a). They are controlled from the CPU by means of chip-internal LCD pins DB7 to DB0, RS, R/W, and STRB, via chip-internal I/O ports 9 and A. The pin configuration is shown in table 13.5, and an example of the timing for access to registers in the LCD controller is shown in figure 13.3. For information on port 9 and port A, see the descriptions in section 8, I/O Ports. Table 13.5 Pin Configuration Pin Name Data bus pins Register selector pin Read/write select pin Strobe pin Abbr. DB7 to DB0 RS R/W STRB I/O I/O Input Input Input Function When R/W = 0, these pins input data to be written to a register; when R/W = 1, they output data read from a register When R/S = 0, the index register is selected; when RS = 1, a control register is selected When R/W = 0, write access is selected; when R/W = 1, read access is selected At the fall of STRB, read or write access, as selected by R/W, is performed on the register selected by RS Writing to Index Register When RS and R/W are both cleared to 0, data DB7 to DB0 is written to the index register (IR) at the falling edge of STRB. Do not change RS or R/W at the fall of STRB. Reading and Writing to Control Registers To access a control register, data indicating the number of the register to be accessed must be written to the index register (IR) before making the access. The register number data to be written to IR is shown in table 13.2. As the register number written to IR is retained until IR is written to again, if the same control register is accessed repeatedly, it is not necessary to write to IR each time. In a write to a control register, when RS has been set to 1 and R/W cleared to 0, data DB7 to DB0 is written to the control register specified by the index register (IR) at the falling edge of STRB. Except for the display data register (LR4), control registers cannot be read. In a read of LR4, when the LR4 register number is written to the index register (IR), and RS and R/W are both set to 1, DB7 to DB0 are set to output mode, and the display memory data at the address specified by the address register (LR2) is output from DB7 to DB0 at the rising edge of STRB. If a read is also performed in the next cycle, the data output is held until the next rise of STRB, but if a write is Rev.3.00 Jul. 19, 2007 page 343 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) performed in the next cycle, DB7 to DB0 are set to input mode from the point at which R/W is cleared to 0, and the output is cleared. In either case, do not change RS or R/W at the fall of STRB. RS R/W STRB DB7 to DB0 Data Data Data Data Data Data Index Data Index Data Data Data register write register write register write register read register read register write Figure 13.3 Example of Timing Sequence for 8-Bit Data Transfer Notes on Use of Chip-Internal I/O Ports For LCD controller interface internal ports 9 and A, port input/output is controlled by means of PCR9 and PCRA in the same way as for ordinary I/O ports, and in output mode, the values set in PDR9 or PDRA are output. Also, LCD controller internal pins RS, R/W, and STRB are input-only pins, and DB7 to DB0 input/output is controlled by R/W. Therefore, the following points must be noted. 1. After reset release and standby mode release Since the chip's internal I/O ports go to the high-impedance state in a reset and in standby mode, in initialization after reset or standby mode release, H'06 should be set in PDRA, and H'07 in PCRA. This will set port A to output mode. If the PDRA setting were H'00, there would be a possibility of the index register (IR) being written to. 2. Changing register read/write setting When an LCD controller register is read (R/W = 1), DB7 to DB0 output data from the LCD controller side, and so port 9 must be set to input mode. Therefore, H'00 must be written to PCR9, setting port 9 to input mode, before changing the R/W setting from 0 to 1. When writing data to an LCD controller register, first change R/W from 1 to 0, then write H'FF to PCR9, setting port 9 to output mode. Rev.3.00 Jul. 19, 2007 page 344 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Examples of display data register (LR4) read/write access when read-modify-write is designated are shown below. [Set index register to display data register] * Port A set to output mode, RMW set to 1 MOV.W MOV.W MOV.B MOV.B MOV.B MOV.B MOV.B #H'0100,R1 #H'04FF,R0 R1L,@PDRA ............. Clear R/W to 0 R0H,@PDR9 R0L,@PCR9 ............. Output H'04 from port 9 R1H,@PDRA R1L,@PDRA ............. Write H'04 to index register [Read display data register] MOV.B MOV.W MOV.B MOV.B MOV.B MOV.B R1L,@PCR9 ............. Set port 9 to input mode #H'0706, R2 R2L,@PDRA ............. Set R/W to 1 R2H,@PDRA @PDR9, R0H ............ Read PDR9 into general register R2L,@PDRA [Write to display data register] MOV.W MOV.B NOT.B MOV.B MOV.B MOV.B MOV.B #H'0504,R3 R3L,@PDRA ............. Clear R/W to 0 R0H R0H,@PDR9 R0L,@PCR9 ............. Set port 9 to output mode R3H,@PDRA R3L @PDRA ............. Write data to display data register ............. Invert general register data Rev.3.00 Jul. 19, 2007 page 345 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.3 LCD Drive Pin Functions Common/Segment Output Switching Among the LCD controller's LCD drive outputs, COM9 to COM32 and SEG64 to SEG41 are switched according to the display duty and display mode. The display duty is set by control register 1 (LR0) bits DDTY1 and DDTY0, and the display mode by bit SOB. (1) When SOB = 0 (character display mode) * 1/8 duty (DDTY1 = 1) Common outputs: COM1 to COM8 Segment outputs: SEG1 to SEG40 Note: COM9/SEG64 to COM16/SEG57 output common signal non-selection waveforms, COM17/SEG56 to COM24/SEG49 output the same waveforms as COM1 to COM8, and COM25/SEG48 to COM32/SEG41 output common signal non-selection waveforms. * 1/16 duty (DDTY1 = 0, DDTY0 = 1) Common outputs: COM1 to COM16 Segment outputs: SEG1 to SEG40 Note: COM17/SEG56 to COM32/SEG41 output the same waveforms as COM1 to COM16. * 1/32 duty (DDTY1 = 0, DDTY0 = 0) Common outputs: COM1 to COM32 Segment outputs: SEG1 to SEG40 (2) When SOB = 1 (graphic display mode) * 1/8 duty (DDTY1 = 1) Common outputs: COM1 to COM8 Segment outputs: SEG1 to SEG64 * 1/16 duty (DDTY1 = 0, DDTY0 = 1) Common outputs: COM1 to COM16 Segment outputs: SEG1 to SEG56 * 1/32 duty (DDTY1 = 0, DDTY0 = 0) Common outputs: COM1 to COM32 Segment outputs: SEG1 to SEG40 Rev.3.00 Jul. 19, 2007 page 346 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Table 13.6 Pin Functions According to Display Mode and Display Duty Function SOB = 0 (Character Display Mode) Pin Name COM1 to COM8 COM9/SEG64 to COM16/SEG57 SEG1 to SEG40 1/8 Duty 1/16 Duty 1/32 Duty COM1 to COM16 SOB = 1 (Graphic Display Mode) 1/8 Duty COM1 to COM8 SEG64 to SEG57 SEG1 to SEG40 SEG1 to SEG56 SEG1 to SEG56 SEG1 to SEG40 COM32 to COM17 1/16 Duty 1/32 Duty COM1 to COM16 COM1 to COM16 COM1 to COM8 COM1 to COM16 Common signal non-selection waveform SEG1 to SEG40 SEG1 to SEG40 COM32/SEG41 to Common signal COM25/SEG48 non-selection waveform COM24/SEG49 to COM8 to COM1 COM17/SEG56 COM16 to COM32 to COM1 COM17 13.3.4 Display Memory Configuration and Display The LCD controller includes 64 x 32-bit bit-mapped display memory. As the display memory configuration, a 5-bit x 8 or 8-bit x n (n = 5, 7, or 8) X-direction combination can be selected, while the Y-direction configuration is 32 bits. Display data written from the CPU is stored horizontally with the MSB at the left and the LSB at the right, as shown in figure 13.4. On the display, 1 data corresponds to illumination (black), and 0 data to non-illumination (colorless). Rev.3.00 Jul. 19, 2007 page 347 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) COM1 COM2 LCD SEG1 SEG2 SEG3 SEG4 SEG5 SEG40 Y address H'00 H'01 DB7 (MSB) 0 1 1 0 0 1 1 0 0 1 DB0 (LSB) Display memory (1) SOB = 0 COM1 COM2 LCD SEG1 SEG3 SEG5 SEG7 Y address H'00 H'01 1 0 SEG2 SEG4 SEG6 SEG8 0 1 1 0 0 1 1 0 0 1 1 0 0 1 DB0 (LSB) Display memory SEG40, SEG56, SEG64 DB7 (MSB) (2) SOB = 1 Figure 13.4 Memory Data and Display Rev.3.00 Jul. 19, 2007 page 348 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.5 Display Data Output The LCD controller has a character display mode (SOB = 0) in which only 5 bits of each display data byte can be output to perform efficient 5-dot x 8-dot character output, and a graphic display mode (SOB = 1) in which all the bits of a data byte can be output to perform efficient full-dot graphic display. The relationship between the display duty and output pins in each mode is shown in figure 13.5. Rev.3.00 Jul. 19, 2007 page 349 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) (1) Character display mode (SOB = 0) * 1/8 duty Display dots: 320 X address H'00 H'00 H'05 H'06 H'07 Y address H'07 H'08 H'0F H'10 H'1F SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 * 1/16 duty Display dots: 640 X address H'00 H'00 H'05 H'06 H'07 Y address H'07 H'08 H'0F H'10 H'1F SEG36 SEG37 SEG38 SEG39 SEG40 COM16 COM15 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 Valid display data area Figure 13.5 Display Duty and Valid Display Data Area (1) Rev.3.00 Jul. 19, 2007 page 350 of 532 REJ09B0397-0300 COM2 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG36 SEG37 SEG38 SEG39 SEG40 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 13. Dot Matrix LCD Controller (H8/3857 Group) * 1/32 duty Display dots: 1280 X address H'00 H'00 H'05 H'06 H'07 Y address H'07 H'08 H'0F H'10 H'1F SEG36 SEG37 SEG38 SEG39 SEG40 COM32 COM31 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 (2) Graphic display mode (SOB = 1) * 1/8 duty Display dots: 512 X address H'00 H'00 H'05 H'06 H'07 Y address H'07 H'08 H'0F H'10 H'1F SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 Valid display data area Figure 13.5 Display Duty and Valid Display Data Area (2) Rev.3.00 Jul. 19, 2007 page 351 of 532 REJ09B0397-0300 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM2 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 Y address H'07 H'08 H'00 H'1F H'0F H'10 H'07 H'08 H'00 H'1F H'00 H'00 H'0F H'10 * 1/16 duty Display dots: 896 * 1/32 duty Display dots: 1280 Y address Rev.3.00 Jul. 19, 2007 page 352 of 532 REJ09B0397-0300 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 H'05 X address X address H'05 H'06 H'06 H'07 H'07 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 13. Dot Matrix LCD Controller (H8/3857 Group) SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 Valid display data area Figure 13.5 Display Duty and Valid Display Data Area (3) SEG39 SEG40 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.6 Register and Display Memory Access Register Access To access a register, RS is first cleared to 0 and the register number of the register to be accessed is set in the index register. Then RS is set to 1, enabling the specified register to be accessed. Some internal registers have nonexistent bits; 0 must be written to these bits. The display data register (LR4) is the only register that can be read. Display Memory Access To access the display memory, the address to be accessed is set in the address register (LR2). The memory is then accessed via the display data register (LR4). This access can be performed without awareness of the display-side read. See figure 13.6 for the procedure. After the respective display data register (LR4) accesses, the X and Y addresses are automatically incremented on the basis of the value set in the INC bit in control register 2 (LR1), and therefore address settings need not be made each time. With 1/32 duty (DDTY1 = 0, DDTY0 = 0) in graphic display mode (SOB = 1), if INC = 0 the X address remains the same in each read/write access to the display data register (LR4), while the Y address is automatically incremented up to H'1F. After reaching H'1F, the Y address returns to H'00 again, and the X address is simultaneously incremented. If INC = 1, on the other hand, the Y address remains the same in each read/write access to the display data register (LR4), while the X address is automatically incremented up to H'4. After reaching H'4, the X address returns to H'0 again, and the Y address is simultaneously incremented. In this way, consecutive read/write accesses can be made to the entire display memory area. Rev.3.00 Jul. 19, 2007 page 353 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) X addres H'0 H'00 Y address H'1 H'4 H'01 H'1F (1) Priority given to Y-direction data access (INC = 0) X address H'0 H'00 Y address H'1 H'4 H'01 H'1F (2) Priority given to X-direction data access (INC = 1) Notes: 1. Address register (LR2) bits XA2 to XA0 show the X address, and bits YA4 to YA0 show the Y address. 2. X address operation (1) SOB = 0: Address becomes H'0 after H'7, regardless of the display duty. (2) SOB = 1: Address becomes H'0 after H'6 when 1/16 duty is set, and after H'7 when 1/8 duty is set. 3. Y address operation Address becomes H'00 after H'0F when 1/16 duty is set, and after H'07 when 1/8 duty is set. Figure 13.6 Display Memory Access Methods (SOB = 1, 1/32 Duty) Rev.3.00 Jul. 19, 2007 page 354 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Reading for Display The LCD controller's display RAM is of the dual-port type, with accesses from the CPU and reads for LCD display independent of each other. This allows flexible interfacing. RS R/W STRB Input data H'02 [n, m] H'04 Output data data [n, m] data [n, m+1] Address [*,*] [n, m] [n, m+1] [n, m+2] Figure 13.7 Memory Read Procedure Rev.3.00 Jul. 19, 2007 page 355 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Read-Modify-Write Mode In the normal state, the X or Y address is incremented after both read and write accesses to the display memory. In read-modify-write mode, the address is incremented only after a write, and remains the same after a read. By using this mode, it is possible to read previously written data, process that data, and then write it back to the same address. START Set address Read data Write data (Address) + 1 No End of modification? Yes END Figure 13.8 Read-Modify-Write Mode Flowchart 13.3.7 Scroll Function The LCD controller allows vertical scrolling of any number of lines to be performed by specifying the display start line. Figure 13.9 shows the relationship between the display memory and Y address, and the display memory and LCD display after scrolling, for 1/16 duty and 1/8 duty settings. If the display start address is set to H'01, the data at Y address H'00 is displayed in the 16th line. Therefore, when the display is scrolled in order to show the next screen, the data at Y address H'00 must be rewritten with the next display data. This data update should be carried out after the display is scrolled. Rev.3.00 Jul. 19, 2007 page 356 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Display start line = 0 Y address H' 00 H' 01 H' 02 H' 03 H' 04 H' 05 H' 06 H' 07 H' 08 H' 09 H' 0A H' 0B H' 0C H' 0D H' 0E H' 0F Y address H' 00 H' 01 H' 02 H' 03 H' 04 H' 05 H' 06 H' 07 Display start line = 1 Y address H' 01 H' 02 H' 03 H' 04 H' 05 H' 06 H' 07 H' 08 H' 09 H' 0A H' 0B H' 0C H' 0D H' 0E H' 0F H' 00 Y address H' 01 H' 02 H' 03 H' 04 H' 05 H' 06 H' 07 H' 00 Display start line = 2 Y address H' 02 H' 03 H' 04 H' 05 H' 06 H' 07 H' 08 H' 09 H' 0A H' 0B H' 0C H' 0D H' 0E H' 0F H' 00 H' 01 Y address H' 02 H' 03 H' 04 H' 05 H' 06 H' 07 H' 00 H' 01 (1) 1/16 duty (2) 1/8 duty Note: The Y address comprises bits YA4 to YA0 in the address register (LR2). Figure 13.9 Vertical Scrolling Rev.3.00 Jul. 19, 2007 page 357 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.8 Blink Function Dot Matrix Display Blinking The LCD controller can perform blinking display in any area. With an 80 Hz frame frequency, the display goes on and off in a cycle of approximately 1.6 seconds. To set a blink area, in the horizontal direction the line unit is specified by means of the blink start line register (LR8) and blink end line register (LR9), while in the vertical direction a 5-bit unit (SOB = 0) or 8-bit unit (SOB = 1) is set in the blink register (LR6). When 1 is set in the blink register (LR6), blinking of the corresponding dot is controlled. After making these register settings, blinking is started by setting the BLK bit in control register 2 (LR1) to 1. As the blink area is designated by an absolute specification with respect to the display memory, if the display is scrolled the blink area also shifts accordingly. LCD Blink start line register (LR8) Blink end line register (LR9) SOB = 0 SOB = 1 SEG1 SEG6 SEG11 SEG16 SEG21 SEG26 SEG31 SEG36 SEG17 SEG25 SEG33 SEG41 SEG49 SEG57 SEG1 SEG9 Blink register (LR6) 1 1 1 0 0 1 1 0 DB7 (MSB) Blink area DB0 (LSB) Figure 13.10 Blink Register (LR6) and Blink Locations Rev.3.00 Jul. 19, 2007 page 358 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Display start line = H'0 Blink start line = H'0 Blink end line = H'7 Display start line = H'4 Blink start line = H'4 Blink end line = H'7 Figure 13.11 Blinking during Display Scrolling (SOB = 0, 1/16 Duty) Rev.3.00 Jul. 19, 2007 page 359 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.9 Module Standby Mode The LCD controller has a module standby function that enables low power consumption to be achieved. In module standby mode, the built-in step-up circuit and op-amps are halted, and segment and common outputs go to the VSS (display-off state) level. Display RAM and internal register data is retained, except for the DISP and OPON bits in control register 2 (LR1). The control registers can still be accessed in the module standby state. Figure 13.12 shows the procedures for initiating and clearing module standby mode. The initiation and clearing procedures must be followed exactly in order to protect the display memory contents. When the CPU is placed in standby mode, set the LSBY bit in control register 1 (LR0) to 1 before executing the standby instruction. After clearing standby mode, follow the module standby clearing procedure to start display. Initiation Set LSBY to 1 Internal operation halts Step-up operation halts Module standby mode initiated Internal operation starts Step-up operation starts Clearing Clear LSBY to 0 Wait for step-up circuit power supply to stabilize Set OPON to 1 Wait for op-amps to stabilize Set DISP to 1 Display starts Figure 13.12 Module Standby Mode and Standby Mode Initiation and Clearing Procedures Rev.3.00 Jul. 19, 2007 page 360 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.10 Power-On and Power-Off Procedures As the LCD controller incorporates a complete power supply circuit, the procedures shown in figure 13.13 must be followed when powering on and off. Failure to follow these procedures may result in an abnormal display. Starting display Set PWR and OPON* to 1 Set SOB, DDTY1, and DDTY0 according to mode used Step-up operation starts Note: * When the built-in step-up circuit is used, wait for the step-up circuit power supply to stabilize before making this setting. Do not make this setting when using an external power supply. Write data Set DISP to 1 Halting display Clear DISP to 0 Step-up operation halts Clear PWR and OPON to 0 Figure 13.13 Power-On and Power-Off Procedures Rev.3.00 Jul. 19, 2007 page 361 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.11 Power Supply Circuit The LCD controller has a built-in 2X or 3X step-up circuit for LCD drive. In standby mode, the power supply circuit is automatically turned off after a maximum of two subclock cycles, and the power consumption of the step-up circuit falls to zero. The power supply circuit can be turned on and off by a command, and an external power supply circuit should be used if the current capacity of the built-in step-up circuit is insufficient. Step-Up Circuit By inputting the reference voltage to Vci (Vci VCC), connecting a capacitor between VSS and VLOUT, C1+ and C1-, and C2+ and C2-, and setting the PWR bit in control register 1 (LR0) to 1, the potential between Vci and VCC is stepped up by a factor of 2 or 3. See figures 13.17 (1) and (2) for the method of connecting the capacitors. As the subclock is used for voltage step-up, stepup will not be performed unless the subclock is supplied. Since V ci is also used for the step-up circuit power supply, an adequate current must be assured. Step-up cannot be performed below VCC. Apply a V ci voltage that gives a VLOUT level between VCC and 7.0 V. If the step-up circuit is not used, connect V ci to VCC. LCD Drive Level Power Supply Six power supply levelsV1, V2, V3, V3, V4, V5, and VSSare necessary for LCD drive. The V1 to VSS power supplies are normally generated by means of resistive division. The power supply circuit includes a voltage follower op-amp for each voltage level generated by resistive division. When 1/4 bias is used for LCD display, the V3 and V4 pins should be shorted; when 1/5 bias is used, the V3 and V4 pins should be left open. The V34 pin is an internal resistance test pin, and should always be shorted to the V3 pin externally. Contrast Control The LCD controller provides for the following two methods of contrast control. * Using built-in contrast control circuit The LCD controller includes a programmable contrast control circuit. The LCD power supply voltage can be adjusted on the basis of a given step-up circuit voltage by making a selection in the contrast control register (LRA). Rev.3.00 Jul. 19, 2007 page 362 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) * By changing step-up circuit reference voltage Vci The step-up circuit voltage level can be varied by changing step-up circuit reference voltage Vci. External Power Supply * When an external power supply is input to VLCD V1 to V5 can be generated by inputting an external power supply to VLCD, and using the built-in op-amps by setting the OPON bit in control register 2 (LR1) to 1. The VLCD input level must be between VCC and 7.0 V. * When external power supply is input directly to V1 to V5 A power supply can be applied directly to V1, V2, V3, V4, and V5 from an external source by clearing the PWR bit in control register 1 (LR0) and the OPON bit in control register 2 (LR1) to 0, to halt the built-in step-up circuit and cut the built-in op-amp power supply. The same potential as V1 should be input to VLCD. Apply a voltage not exceeding VLCD to V2 through V5. The input level of VLCD and V1 must be between VCC and 7.0 V. In either case, inputting a voltage exceeding the maximum rated voltage may adversely affect the reliability of the chip. 13.3.12 LCD Drive Power Supply Voltages There are six LCD drive power supply voltage valuesV1 to V5, and VSS. V1 is the highest voltage, and VSS the lowest. As shown in figure 13.14, the common waveforms are formed from a combination of V1, V2, V5, and VSS, while the segment waveforms are formed from a combination of V1, V3, V4, and VSS. V1 and VSS are shared by both common and segment waveforms, but the intermediate voltages are different. In figure 13.14, the waveforms of outputs SEG1 to SEG40 differ according to the display data. In this example, LCD panel lines for which COM1 is connected are illuminated, and all other dots are not illuminated. Rev.3.00 Jul. 19, 2007 page 363 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 1 frame V1 V2 V3 COM1 V4 V5 VSS V1 V2 COM2 V3 V4 V5 VSS V1 V2 V3 COM32 V4 V5 VSS Line selection period SEG1 V1 V2 V3 V4 V5 VSS V1 V2 V3 SEG40 V4 V5 VSS Selected Not selected Figure 13.14 LCD Drive Power Supply Waveforms (1/32 Duty) Rev.3.00 Jul. 19, 2007 page 364 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.13 LCD Voltage Generation Circuit When Using External Power Supply and Built-In Op-Amps When the built-in step-up circuit is not used, and the LCD drive voltages are supplied directly from an external power supply, connections should be made as shown in figure 13.15. The VLCD input level must be between VCC and 7.0 V. The LCD controller includes bleeder resistances that generate levels V1 to V5, and voltage follower op-amp circuits. Set the OPON bit in control register 2 (LR1) to 1. Contrast can be controlled by software, using the contrast control register (LRA). If the capacitance of the LCD panel to be driven is large, capacitors of around 0.1 to 0.5 F should be inserted between the V1OUT to V5OUT built-in op-amp outputs and VSS to provide stabilization. In order for the op-amps to operate normally, the contrast control register (LRA) should be set so that the potential difference between VLCD and V1, and between V5 and VSS, is at least 0.4 V. Rev.3.00 Jul. 19, 2007 page 365 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) VLCD VLCD VR V1OUT R OPON = 1 V1 V2OUT V3 V3OUT V34 R V2 SEG1 to SEG40 Rt R V3 Control circuit V4 COM1 to COM8 V5 COM32/SEG41 to COM9/SEG64 V4 V4OUT R 0.1 to 0.5 F + + + + + V5OUT VSS Vci R ON VSS PWR = 0 VCC C1+ C1- C2+ C2- VLOUT VSS Step-up circuit Note: Rt is a test resistance. The V3 and V34 pins should be shorted. Figure 13.15 Example of Connections when Using Built-In Op-Amps and External LCD Power Supply (1/5 Bias) Rev.3.00 Jul. 19, 2007 page 366 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) When Using External Power Supply but Not Using Built-In Op-Amps When the built-in step-up circuit and op-amps are not used, and the LCD drive voltages are supplied directly from an external power supply, connections should be made as shown in figure 13.16. As the built-in step-up circuit and op-amps are not used, the OPON bit in control register 2 (LR1) should be cleared to 0. VLCD VR V1OUT R OPON = 0 V1 V1 V2 V3 V3 V2OUT R V2 SEG1 to SEG40 V3OUT V34 Rt R V3 Control circuit V4 COM1 to COM8 V5 COM32/SEG41 to COM9/SEG64 V4 V4 V4OUT R V5 V5OUT VSS Vci C1+ C1- C2+ C2- VLOUT VSS R OFF VSS PWR = 0 VCC Step-up circuit Notes: 1. Rt is a test resistance. The V3 and V34 pins should be shorted. 2. Set VCC VLCD = V1 7.0 V, and VLCD Vn VSS (n = 2, 3, 4, or 5). Figure 13.16 Example of Connections when Not Using Built-In Op-Amps and Using External LCD Power Supply (1/5 Bias) Rev.3.00 Jul. 19, 2007 page 367 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) When Using Built-In Step-Up Circuit and Op-Amps When the built-in step-up circuit is used, connections should be made as shown in figure 13.17 (1) (3X step-up) or figure 13.17 (2) (2X step-up). The LCD controller includes bleeder resistances that generate levels V1 to V5, and voltage follower op-amp circuits. When the built-in op-amps are used, the OPON bit in control register 2 (LR1) should be set to 1. Contrast can be controlled by software, using the contrast control register (LRA). If the capacitance of the LCD panel to be driven is large, capacitors of around 0.1 to 0.5 F should be inserted between the V1OUT to V5OUT built-in op-amp outputs and VSS to provide stabilization. In order for the op-amps to operate normally, the contrast control register (LRA) should be set so that the potential difference between VLCD and V1, and between V5 and VSS, is at least 0.4 V. Since the Vci pin is also used for the step-up circuit power supply, ensure that an adequate current can be supplied when carrying out reference voltage adjustment. The Vci input level must not exceed VCC. Rev.3.00 Jul. 19, 2007 page 368 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) VLCD VR V1OUT R OPON = 1 V1 V2OUT V3 V3OUT V34 R V2 SEG1 to SEG40 Rt R V3 Control circuit V4 COM1 to COM8 V5 COM32/SEG41 to COM9/SEG64 V4 V4OUT R 0.1 to 0.5 F + + + + + V5OUT VSS Vci R ON VSS PWR = 1 Vci 0.47 to 1 F 0.47 to 1 F + VSS + C1+ C1- C2+ C2- VLOUT Step-up circuit + 0.47 to 1 F Notes: 1. Rt is a test resistance. The V3 and V34 pins should be shorted. 2. The output voltage after step-up should not be lower than VCC and should not exceed 7.0 V. With 3X step-up, in particular, do not input a voltage of 2.3 V or 3. above as the reference voltage (Vci). Vci is also used for the step-up circuit power supply. Use a transistor, etc., for 4. current amplification to ensure an adequate LCD drive current. 5. The Vci input level must not exceed VCC. Care is required with connection when using capacitors with polarity. Figure 13.17 Example of Connections when Using Built-In Step-Up Circuit (1) (3X Step-Up, 1/5 Bias) Rev.3.00 Jul. 19, 2007 page 369 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) VLCD VR V1OUT R OPON = 1 V1 V2OUT V3 V3OUT V34 R V2 SEG1 to SEG40 Rt R V3 Control circuit V4 COM1 to COM8 V5 COM32/SEG41 to COM9/SEG64 V4 V4OUT R 0.1 to 0.5 F + + + + + V5OUT VSS Vci C1+ R ON VSS PWR = 1 Vci 0.47 to 1 F + C1- C2+ C2- VLOUT Step-up circuit 0.47 to 1 F + VSS Notes: 1. 2. 3. 4. 5. Rt is a test resistance. The V3, V34, and V4 pins should be shorted. The output voltage after step-up should not be lower than VCC and should not exceed 7.0 V. Vci is also used for the step-up circuit power supply. Use a transistor, etc., for current amplification to ensure an adequate LCD drive current. The Vci input level must not exceed VCC. Care is required with connection when using capacitors with polarity. Figure 13.17 Example of Connections when Using Built-In Step-Up Circuit (2) (2X Step-Up, 1/4 Bias) Rev.3.00 Jul. 19, 2007 page 370 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) When Using Built-In Step-Up Circuit and Bleeder Resistances If the drive capability of the built-in op-amps is insufficient for the size of the LCD panel, the V1 to V5 levels can be supplied from external bleeder resistances. In this case, clear the OPON bit in control register 2 (LR1) to 0 to turn the op-amps off. The built-in contrast control circuit cannot be used, so contrast control must be handled by an external circuit. A 1/4 or 1/5 bias value can be set, according to the method of connecting the external bleeder resistances. Figure 13.18 shows an example of the connections for 1/5 bias drive. The 2X or 3X step-up circuit can be used. Rev.3.00 Jul. 19, 2007 page 371 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) VLCD OPON = 0 VR V1OUT R V3 R V34 R V4 V4OUT R V5OUT R VSS Vci 0.47 to 1 F 0.47 to 1 F + VSS Notes: 1. Rt is a test resistance. The V3 and V34 pins should be shorted. 2. A value of around 5 k to 25 k is recommended for external power supply division resistance R. 3. For contrast control, either insert a variable resistance between VLCD and V1, or adjust step-up circuit reference voltage Vci. The built-in contrast control circuit cannot be used. 4. The output voltage after step-up should not be lower than VCC and should not exceed 7.0 V. With 3X step-up, in particular, do not input a voltage of 2.3 V or above as the reference voltage (Vci). 5. Vci is also used for the step-up circuit power supply. Use a transistor, etc., for current amplification to ensure an adequate LCD drive current. 6. The Vci input level must not exceed VCC. 7. Care is required with connection when using capacitors with polarity. 8. Set V1OUT VLCD. + C1+ C1- + C2+ C2- VLOUT 0.47 to 1 F Step-up circuit OFF V1 V2 V2OUT SEG1 to SEG40 V3OUT Rt V3 Control circuit V4 COM1 to COM8 V5 COM32/SEG41 to COM9/SEG64 VSS PWR = 1 Vci Figure 13.18 Example of Connections when Using 3X Step-Up Circuit and External Bleeder Resistances (1/5 Bias) Rev.3.00 Jul. 19, 2007 page 372 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.14 Contrast Control Circuit Contrast control can be performed by software (electronic control function) by controlling the LCD drive voltage (the potential difference between VLCD and V1) by means of the contrast control register (LRA). Variable resistance value VR can be adjusted within the range of 0.1 R to 1.6 R, where R is the value of the basic dividing bleeder resistance between VLCD and V1. The contrast control settings by bits CCR3 to CCR0 in the contrast control register (LRA) are shown in table 13.7. To ensure stable operation of the voltage follower op-amp circuits that output levels V1 to V5, the contrast control register (LRA) should be set so that the potential difference between VLCD and V1, and between V5 and VSS, is at least 0.4 V. The contrast control ranges are shown in table 13.8. If contrast control cannot be adequately performed by means of on-chip resistance VR, control can be performed by inserting a resistance between VLOUT and VLCD. Table 13.7 Contrast Control Settings Contrast Control Register (LRA) Variable Resistance CCR3 0 CCR2 0 CCR1 0 CCR0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Value (VR) 1.6R 1.5R 1.4R 1.3R 1.2R 1.1R 1.0R 0.9R 0.8R 0.7R 0.6R 0.5R 0.4R 0.3R 0.2R 0.1R Large Dark V1-VSS Potential Difference Small Display Color Light Rev.3.00 Jul. 19, 2007 page 373 of 532 REJ09B0397-0300 13. Dot Matrix LCD Controller (H8/3857 Group) Table 13.8 Contrast Control Ranges Bias LCD Drive Voltage: VDR Contrast Control Range * LCD drive voltage adjustment range: 1/5 bias drive 5xR x (VLCD - VSS) 5 x R + VR * V5-VSS potential difference limit: 0.758 x (VLCD - VSS) VDR 0.980 x (VLCD - VSS) R x (VLCD - VSS) 0.4 [V] 5 x R + VR VR * VLCD-V1 potential x (VLCD - VSS) 0.4 [V] difference limit: 5 x R + VR * LCD drive voltage adjustment range: 1/4 bias drive 4xR x (VLCD - VSS) 4 x R + VR * V5-VSS potential difference limit: 0.714 x (VLCD - VSS) VDR 0.976 x (VLCD - VSS) R x (VLCD - VSS) 0.4 [V] 4 x R + VR VR * VLCD-V1 potential x (VLCD - VSS) 0.4 [V] difference limit: 4 x R + VR 13.3.15 LCD Drive Bias Selection Circuit The ideal bias value that gives the best contrast is calculated using the equation shown below. If drive is performed at a bias value lower than the optimum, contrast will deteriorate, but the LCD drive voltage (the potential difference between V1 and VSS) can be kept low. If the LCD drive voltage is inadequate even with a low Vci voltage and use of the 3X step-up circuit, or if the output voltage falls and the LCD display becomes faint as batteries wear out, for instance, the display can be made clearer by decreasing the LCD drive bias. Optimum bias value for 1/N duty drive = 1 N+1 Notes: 1. When using 1/5 bias, leave the V3 and V4 pins open. 2. When using 1/4 bias, short the V3 and V4 pins. 3. The V3 and V34 pins must always be shorted. Rev.3.00 Jul. 19, 2007 page 374 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) Section 14 Dot Matrix LCD Controller (H8/3854 Group) 14.1 Overview The LCD controller has built-in display RAM, and performs dot matrix LCD display. One bit of display RAM data corresponds to illumination or non-illumination of one dot on the LCD panel, making possible displays with an extremely high degree of freedom. The LCD controller incorporates all the functions required for LCD display, allowing a dot matrix display of up to 40 x 16 dots. I/O ports are used for the interface with the CPU, offering excellent software heritability when using a combination of MPU and LCD driver. This module operates on the subclock, making it ideal for use in small portable devices. 14.1.1 Features * Built-in bit-mapped display RAM (640 bits) Maximum of 640 display bits (selectable from 40 x 16 bits or 40 x 8 bits) * Choice of 1/8 or 1/16 duty * Low power consumption enabling extended drive on battery power Subclock operation Module standby * Comprehensive display control functions Display data read/write, display on/off control, read-modify-write * CPU interface I/O port interface * Built-in LCD power supply bleeder resistance circuit Rev.3.00 Jul. 19, 2007 page 375 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the LCD controller. COM9 COM1 COM16 COM8 SEG40 SEG1 Segment driver Common driver Decoder Common counter Latch 2 Latch 1 MPX 40 x 16-bit display memory X decoder Display data register Y decoder Display line counter Address register Control register 1/2 Index register Frame frequency setting register LCD drive level power supply selection circuit CPU interface V5OUT V3OUT V1OUT V4OUT V2OUT RS STRB DB6 DB4 DB2 DB0 R/W DB7 DB5 DB3 DB1 Figure 14.1 Block Diagram of LCD Controller Rev.3.00 Jul. 19, 2007 page 376 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.1.3 Pin Configuration Table 14.1 shows the pins assigned to the LCD controller. Table 14.1 Pin Configuration Pin Name Common output pins Segment output pins LCD drive power supply level Abbr. COM1 to COM16 SEG1 to SEG40 I/O Function Output LCD common drive pins Output LCD segment drive pins LCD drive power supply level input/output pins V1OUT to V5OUT I/O 14.1.4 Register Configuration The LCD controller has one index register and five control registers, all of which are accessed via an I/O port interface. Except for the display data register (LR4), these registers cannot be read. The LCD controller register configuration is shown in table 14.2. Table 14.2 Register Configuration Index Register Name Index register Control register 1 Control register 2 Address register Frame frequency setting register Display data register Abbr. IR LR0 LR1 LR2 LR3 LR4 R/W W W W W W R/W 1 0 1 RS 0 1 IR2 0 IR1 0 IR0 0 1 0 1 0 Rev.3.00 Jul. 19, 2007 page 377 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.2 14.2.1 Bit Register Descriptions Index Register (IR) 7 6 5 4 3 2 IR2 0 W 1 IR1 0 W 0 IR0 0 W Initial value Read/Write IR is an 8-bit write-only register that selects one of the LCD controller's five control registers. IR is selected when RS is 0. Upon reset, IR is initialized to H'00. Bits 7 to 3--Reserved Bits: Bits 7 to 3 are reserved; they should always be cleared to 0. Bits 2 to 0--Index Register (IR2 to IR0): Bits 2 to 0 are used to select one of the LCD controller's five control registers. The correspondence between the settings of IR2 to IR0 and the selected registers is shown in table 14.2. Other settings are invalid. 14.2.2 Bit Control Register 1 (LR0) 7 6 5 LSBY 0 W 4 3 2 1 DDTY1 0 W 0 Initial value Read/Write LR0 is an 8-bit write-only register that performs LCD module standby mode setting and drive duty selection. Upon reset, LR0 is initialized to H'00. Bits 7 and 6--Reserved Bits: Bits 7 and 6 are reserved; they should always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 378 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) Bit 5--Module Standby (LSBY): Bit 5 is the module standby setting bit. When LSBY is set to 1, the LCD controller enters standby mode. At this time, bits DISP, LPS1, and LPS0 in LR1 are reset. Bit 5: LSBY Description 0 1 LCD controller operates normally (initial value) Power supply to built-in bleeder resistances halts, display is turned off, and LCD controller enters standby mode Bits 4 to 2--Reserved Bits: Bits 4 to 2 are reserved; they should always be cleared to 0. Bit 1--Display Duty Select (DDTY1): Bit 1 selects a display duty of 1/16 or 1/8. Bit 1: DDTY1 Description 0 1 1/16 duty selected 1/8 duty selected Y address H'8 to H'F display data is invalid (initial value) Bit 0--Reserved Bit: Bit 0 is reserved; it should always be cleared to 0. 14.2.3 Bit Control Register 2 (LR1) 7 6 DISP 0 W 5 LPS1 0 W 4 LPS0 0 W 3 RMW 0 W 2 1 INC 0 W 0 Initial value Read/Write LR1 is an 8-bit write-only register that selects operation or halting of LCD display and supply or halting of current to the built-in bleeder resistances, performs read-modify-write mode setting, and selects the address to be incremented in the display memory. Upon reset, LR1 is initialized to H'00. Bit 7--Reserved Bit: Bit 7 is reserved; it should always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 379 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) Bit 6--LCD Operation Setting (DISP): Bit 6 selects operation or halting of the LCD display. When the LSBY bit in LR0 is set to 1, DISP is cleared. Bit 6: DISP 0 1 Description LCD is turned off. All LCD outputs go to the VSS level LCD is turned on (initial value) Bits 5 and 4--LCD Power Supply Setting (LPS1, LPS0): Bits 5 and 4 specify use or non-use of the internal power supply as the LCD drive power supply, and of the built-in LCD power supply bleeder resistances. When LPS1 is set to 1, the internal power supply is connected to the bleeder resistances. When LPS0 is set to 1, a power supply divided by the built-in bleeder resistances is supplied. When the LCD drive power supply level is applied to V1OUT through V5OUT from an external source, LPS1 and LPS0 must be cleared to 0. When the LSBY bit in LR0 is set, LPS1 and LPS0 are cleared. Bit 5: LPS1 0 1 Description Power supply to V1OUT is halted Power supply voltage is supplied to V1OUT (initial value) Bit 4: LPS0 0 1 Description Built-in bleeder resistances not used Built-in bleeder resistances used (initial value) Bit 3--Read-Modify-Write Setting (RMW): Bit 3 selects whether display memory X or Y address incrementing is carried out after a write/read access, or only after a write access (readmodify-write mode). Bit 3: RMW 0 1 Description Address is incremented after write/read access to display memory (initial value) Read-modify-write mode is set In this mode, address is incremented only after write access to display memory Bit 2--Reserved Bit: Bit 2 is reserved; it should always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 380 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) Bit 1--Increment Address Select (INC): Bit 1 selects either the X address or the Y address as the address to be incremented after the display memory access specified by the RMW bit. The selected address is cleared after a display memory access with the maximum value for the valid display data area; in this case the other address is incremented. Bit 1: INC 0 1 Description Incrementing of display memory Y address has priority; X address is incremented after Y address overflow (initial value) Incrementing of display memory X address has priority; Y address is incremented after X address overflow Bit 0--Reserved Bit: Bit 0 is reserved; it should always be cleared to 0. 14.2.4 Bit Address Register (LR2) 7 XA2 6 XA1 0 W 5 XA0 0 W 4 3 YA3 0 W 2 YA2 0 W 1 YA1 0 W 0 YA0 0 W Initial value Read/Write 0 W LR2 is an 8-bit write-only register that sets the display memory X- and Y-direction addresses accessed by the CPU. Upon reset, LR2 is initialized to H'00. Bits 7 to 5--X Address Setting (XA2 to XA0): Bits 7 to 5 set the display memory X-direction address. A value from H'0 to H'4 can be set. Do not perform access in the range H'5 to H'7. When the INC bit in LR1 is set to 1, the address is automatically incremented after the access specified by the RMW bit in LR1, and is cleared after an H'4 access. When INC is 0 and YA3 to YA0 represent the maximum value for the valid display data area, the address is incremented after the access specified by RMW. Bit 4--Reserved Bit: Bit 4 is reserved; it should always be cleared to 0. Bits 3 to 0--Y Address Setting (YA3 to YA0): Bits 3 to 0 set the display memory Y-direction address. A value from H'0 to H'F can be set, but display data from H'8 to H'F is invalid with 1/8 duty. When the INC bit in LR1 is cleared to 0, the address is automatically incremented after the access specified by the RMW bit in LR1, and is cleared after an access with the maximum value for the Rev.3.00 Jul. 19, 2007 page 381 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) valid display data area. When INC is 1 and the value in XA2 to XA0 is H'4, the address is incremented after the access specified by RMW. 14.2.5 Bit Frame Frequency Setting Register (LR3) 7 6 5 4 3 2 FS2 0 W 1 FS1 0 W 0 FS0 0 W Initial value Read/Write LR3 is an 8-bit write-only register that sets the frame frequency. Upon reset, LR3 is initialized to H'00. Bits 7 to 3--Reserved Bits: Bits 7 to 3 are reserved; they should always be cleared to 0. Bits 2 to 0--Frame Frequency Setting (FS2 to FS0): Bits 2 to 0 control the subclock division ratio and set the LCD frame frequency. The relationship between the LCD frame frequency fF (Hz), the subclock frequency fW (Hz), the division ratio r, and the LCD duty 1/N is as follows: fF = fW rxN Set a division ratio suitable for the characteristics of the LCD panel used. The correspondence between register settings, division ratios, and frame frequencies at each display duty is shown in table 14.3. Rev.3.00 Jul. 19, 2007 page 382 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) Table 14.3 Register Settings, Division Ratios, and Frame Frequencies at Each Display Duty Display Duty 1/N 1/8 1/16 Subclock Frequency fW (kHz) FS2 0 FS1 0 FS0 0 1 1 0 1 1 0 0 1 1 0 1 Division ratio r 2 4 8 16 32 64 128 Setting prohibited 32.768 38.4 32.768 38.4 Frame Frequency fF (Hz) 2048.0 1024.0 512.0 256.0 128.0 64.0 32.0 Setting prohibited 2400.0 1200.0 600.0 300.0 150.0 75.0 37.5 Setting prohibited 1024.0 512.0 256.0 128.0 64.0 32.0 16.0 Setting prohibited 1200.0 600.0 300.0 150.0 75.0 37.5 18.8 Setting prohibited 14.2.6 Bit Display Data Register (LR4) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Initial value Read/Write Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W LR4 is an 8-bit read/write register used to perform read/write access to the display memory specified by XA2 to XA0 and YA3 to YA0 in LR2. In a write to display memory, the write is performed directly to the display memory via this register. In a read, the data is temporarily latched into this register before being output to the bus. After a reset, the display memory and LR4 contents are undefined. Rev.3.00 Jul. 19, 2007 page 383 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3 14.3.1 Operation System Overview The LCD controller operates at 1/16 or 1/8 duty. The display size is a maximum of 40 x 16 dots. As the LCD controller operates on the subclock to perform display control, the time, etc., can be constantly displayed. Also, since data in the display RAM is retained even in module standby mode, low power consumption can be achieved without affecting the display. H8/3854 RS R/W CPU STRB DB7 to DB0 COM1 to COM16 LCD panel LCD controller SEG1 to SEG40 Figure 14.2 System Block Diagram Rev.3.00 Jul. 19, 2007 page 384 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.2 CPU Interface The LCD controller's registers are not included in the memory map shown in figure 2.16 (b). They are controlled from the CPU by means of chip-internal LCD pins DB7 to DB0, RS, R/W, and STRB, via chip-internal I/O ports 9 and A. The pin configuration is shown in table 14.4, and an example of the timing for access to registers in the LCD controller is shown in figure 14.3. For information on port 9 and port A, see the descriptions in section 8, I/O Ports. Table 14.4 Pin Configuration Pin Name Data bus pins Register selector pin Read/write select pin Strobe pin Abbr. DB7 to DB0 RS R/W STRB I/O I/O Input Input Input Function When R/W = 0, these pins input data to be written to a register; when R/W = 1, they output data read from a register When R/S = 0, the index register is selected; when RS = 1, a control register is selected When R/W = 0, write access is selected; when R/W = 1, read access is selected At the fall of STRB, read or write access, as selected by R/W, is performed on the register selected by RS Writing to Index Register When RS and R/W are both cleared to 0, data DB7 to DB0 is written to the index register (IR) at the falling edge of STRB. Do not change RS or R/W at the fall of STRB. Reading and Writing to Control Registers To access a control register, data indicating the number of the register to be accessed must be written to the index register (IR) before making the access. The register number data to be written to IR is shown in table 14.2. As the register number written to IR is retained until IR is written to again, if the same control register is accessed repeatedly, it is not necessary to write to IR each time. In a write to a control register, when RS has been set to 1 and R/W cleared to 0, data DB7 to DB0 is written to the control register specified by the index register (IR) at the falling edge of STRB. Except for the display data register (LR4), control registers cannot be read. In a read of LR4, when the LR4 register number is written to the index register (IR), and RS and R/W are both set to 1, DB7 to DB0 are set to output mode, and the display memory data at the address specified by the address register (LR2) is output from DB7 to DB0 at the falling edge of STRB. If a read is also performed in the next cycle, the data output is held until the next fall of STRB, but if a write is Rev.3.00 Jul. 19, 2007 page 385 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) performed in the next cycle, DB7 to DB0 are set to input mode from the point at which R/W is cleared to 0, and the output is cleared. In either case, do not change RS or R/W at the fall of STRB. RS R/W STRB DB7 to DB0 Data Data Data Data Data Data Index Data Index Data Data Data register write register write register write register read register read register write Figure 14.3 Example of Timing Sequence for 8-Bit Data Transfer Notes on Use of Chip-Internal I/O Ports For LCD controller interface internal ports 9 and A, port input/output is controlled by means of PCR9 and PCRA in the same way as for ordinary I/O ports, and in output mode, the values set in PDR9 or PDRA are output. Also, LCD controller internal pins RS, R/W, and STRB are input-only pins, and DB7 to DB0 input/output is controlled by R/W. Therefore, the following points must be noted. 1. After reset release and standby mode release Since the chip's internal I/O ports go to the high-impedance state in a reset and in standby mode, in initialization after reset or standby mode release, H'06 should be set in PDRA, and H'07 in PCRA. This will set port A to output mode. If the PDRA setting were H'00, there would be a possibility of the index register (IR) being written to. 2. Changing register read/write setting When an LCD controller register is read (R/W = 1), DB7 to DB0 output data from the LCD controller side, and so port 9 must be set to input mode. Therefore, H'00 must be written to PCR9, setting port 9 to input mode, before changing the R/W setting from 0 to 1. When writing data to an LCD controller register, first change R/W from 1 to 0, then write H'FFF to PCR9, setting port 9 to output mode. Rev.3.00 Jul. 19, 2007 page 386 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) Examples of display data register (LR4) read/write access when read-modify-write is designated are shown below. [Set index register to display data register] * Port A set to output mode, RMW set to 1 MOV.W MOV.W MOV.B MOV.B MOV.B MOV.B MOV.B #H'0100,R1 #H'04FF,R0 R1L,@PDRA ............. Clear R/W to 0 R0H,@PDR9 R0L,@PCR9 ............. Output H'04 from port 9 R1H,@PDRA R1L,@PDRA ............. Write H'04 to index register [Read display data register] MOV.B MOV.W MOV.B MOV.B MOV.B MOV.B R1L,@PCR9 ............. Set port 9 to input mode #H'0706, R2 R2L,@PDRA ............. Set R/W to 1 R2H,@PDRA R2L,@PDRA @PDR9, R0H ............ Read PDR9 into general register [Write to display data register] MOV.W MOV.B NOT.B MOV.B MOV.B MOV.B MOV.B #H'0504,R3 R3L,@PDRA ............. Clear R/W to 0 R0H R0H,@PDR9 R0L,@PCR9 ............. Set port 9 to output mode R3H,@PDRA R3L @PDRA ............. Write data to display data register ............. Invert general register data Rev.3.00 Jul. 19, 2007 page 387 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.3 LCD Drive Pin Functions Common/Segment Output The display duty is set by control register 1 (LR0) bits DDTY1. * 1/8 duty (DDTY1 = 1) Common outputs: COM1 to COM8 Segment outputs: SEG1 to SEG40 Note: COM9 to COM16 output common signal non-selection waveforms * 1/16 duty (DDTY1 = 0) Common outputs: COM1 to COM16 Segment outputs: SEG1 to SEG40 Table 14.5 Pin Functions According to Display Duty Function Pin Name COM1 to COM8 COM9 to COM16 SEG1 to SEG40 1/8 Duty COM1 to COM8 Common signal non-selection waveform SEG1 to SEG40 SEG1 to SEG40 1/16 Duty COM1 to COM16 Rev.3.00 Jul. 19, 2007 page 388 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.4 Display Memory Configuration and Display The LCD controller includes 40 x 16-bit bit-mapped display memory. As the display memory configuration, an 8-bit x 5 X-direction combination can be selected, while the Y-direction configuration is 16 bits. Display data written from the CPU is stored horizontally with the MSB at the left and the LSB at the right, as shown in figure 14.4. On the display, 1 data corresponds to illumination (black), and 0 data to non-illumination (colorless). COM1 COM2 LCD SEG1 SEG3 SEG5 SEG7 Y address H'00 H'01 1 0 SEG2 SEG4 SEG6 SEG8 0 1 1 0 0 1 1 0 0 1 1 0 0 1 DB0 (LSB) Display memory SEG40 DB7 (MSB) Figure 14.4 Memory Data and Display Rev.3.00 Jul. 19, 2007 page 389 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.5 Display Data Output The relationship between the LCD controller display duty and output pins is shown in figure 14.5. (1) 1/8 duty Display dots: 320 X address H'0 H'0 H'1 H'2 H'3 H'4 Y address H'7 H'8 H'F (2) 1/16 duty H'00 Y address H'07 H'08 H'1F Rev.3.00 Jul. 19, 2007 page 390 of 532 REJ09B0397-0300 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 Display dots: 640 X address H'0 H'1 H'2 H'3 H'4 Valid display data area Figure 14.5 Display Duty and Valid Display Data Area 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.6 Register and Display Memory Access Register Access To access a register, RS is first cleared to 0 and the register number of the register to be accessed is set in the index register. Then RS is set to 1, enabling the specified register to be accessed. Some internal registers have nonexistent bits; 0 must be written to these bits. The display data register (LR4) is the only register that can be read. Display Memory Access To access the display memory, the address to be accessed is set in the address register (LR2). The memory is then accessed via the display data register (LR4). This access can be performed without awareness of the display-side read. See figure 14.6 for the procedure. After the respective display data register (LR4) accesses, the X and Y addresses are automatically incremented on the basis of the value set in the INC bit in control register 2 (LR1), and therefore address settings need not be made each time. With 1/16 duty (DDTY1 = 0), if INC = 0 the X address remains the same in each read/write access to the display data register (LR4), while the Y address is automatically incremented up to H'F. After reaching H'F, the Y address returns to H'0 again, and the X address is simultaneously incremented. If INC = 1, on the other hand, the Y address remains the same in each read/write access to the display data register (LR4), while the X address is automatically incremented up to H'4. After reaching H'4, the X address returns to H'0 again, and the Y address is simultaneously incremented. In this way, consecutive read/write accesses can be made to the entire display memory area. Rev.3.00 Jul. 19, 2007 page 391 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) X addres H'0 H'0 H'1 H'4 Y address H'1 H'F (1) Priority given to Y-direction data access (INC = 0) X address H'0 H'0 H'1 H'4 Y address H'1 H'F (2) Priority given to X-direction data access (INC = 1) Notes: 1. Address register (LR2) bits XA2 to XA0 show the X address, and bits YA3 to YA0 show the Y address. 2. X address operation Address becomes H'0 after H'4, regardless of the duty. 3. Y address operation Address becomes H'0 after H'0F when 1/16 duty is set, and after H'07 when 1/8 duty is set. Figure 14.6 Display Memory Access Methods (1/16 Duty) Rev.3.00 Jul. 19, 2007 page 392 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) Reading for Display Reads for LCD display are performed asynchronously with respect to accesses by the CPU. However, since simultaneous accesses would corrupt data in the RAM, arbitration is carried out within the chip. Basically, accesses by the CPU have priority, and reads for display are performed in the intervals between CPU accesses. RS R/W STRB Input data H'02 [n, m] H'04 Output data data [n, m] data [n, m+1] Address [*,*] [n, m] [n, m+1] [n, m+2] Figure 14.7 Memory Read Procedure Rev.3.00 Jul. 19, 2007 page 393 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) Read-Modify-Write Mode In the normal state, the X or Y address is incremented after both read and write accesses to the display memory. In read-modify-write mode, the address is incremented only after a write, and remains the same after a read. By using this mode, it is possible to read previously written data, process that data, and then write it back to the same address. START Set address Read data Write data (Address) + 1 No End of modification? Yes END Figure 14.8 Read-Modify-Write Mode Flowchart Rev.3.00 Jul. 19, 2007 page 394 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.7 Module Standby Mode The LCD controller has a module standby function that enables low power consumption to be achieved. In module standby mode, the current supply to the built-in bleeder resistances is halted, and segment and common outputs go to the VSS (display-off state) level. Display RAM and internal register data is retained, except for the DISP, LPS1, and LPS0 bits in control register 2 (LR1). The control registers can still be accessed in the module standby state. Figure 14.9 shows the procedures for initiating and clearing module standby mode. The initiation and clearing procedures must be followed exactly in order to protect the display memory contents. When the CPU is placed in standby mode, set the LSBY bit in control register 1 (LR0) to 1 before executing the standby instruction. After clearing standby mode, follow the module standby clearing procedure to start display. Initiation Set LSBY to 1 Internal operation halts Module standby mode initiated Clearing Clear LSBY to 0 Internal operation starts Set LPS1*, LPS0*, and DISP to 1 Display starts Note: * Do not set to 1 when an external power supply is used. Figure 14.9 Module Standby Mode and Standby Mode Initiation and Clearing Procedures Rev.3.00 Jul. 19, 2007 page 395 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.8 Power-On and Power-Off Procedures As the LCD controller incorporates a complete power supply circuit, the procedures shown in figure 14.10 must be followed when powering on and off. Failure to follow these procedures may result in an abnormal display. Starting display Set DDTY1 according to mode used Write data Set LPS1*, LPS0*, and DISP to 1 Halting display Clear LPS1, LPS0, and DISP to 0 Note: * Do not set to 1 when an external power supply is used. Figure 14.10 Power-On and Power-Off Procedures 14.3.9 Power Supply Circuit The LCD controller has a built-in bleeder resistance circuit for LCD drive. In standby mode, the voltage circuits are automatically turned off and the power consumption of the power supply circuit falls to zero. The power supply circuit can be turned on and off by a command, and an external power supply circuit should be used if the current capacity of the built-in step-up circuit is insufficient. LCD Drive Level Six power supply levelsV1, V2, V3, V3, V4, V5, and VSSare necessary for LCD drive. The V1 to VSS power supplies are normally generated by means of resistive division. When 1/4 bias is used for LCD display, the V3OUT and V4OUT pins should be shorted; when 1/5 bias is used, the V3OUT and V4OUT pins should be left open. Rev.3.00 Jul. 19, 2007 page 396 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) External Power Supply * When external power supply is input directly to pins V1OUT through V5OUT A power supply can be applied directly to V1OUT, V2OUT, V3OUT, V4OUT, and V5OUT from an external source by clearing bits LPS0 and LPS1 to 0 in control register 2 (LR1) to halt the power supply to the built-in bleeder resistance circuit. Apply a voltage not exceeding VCC to pins V1OUT through V5OUT. * When an external power supply is input to pin V1OUT V1 to V5 can be generated by inputting an external power supply to V1OUT, and using the built-in bleeder resistances by setting the LPS1 bit to 1 in control register 2 (LR1). Apply a voltage not exceeding VCC to pin V1OUT. In either case, inputting a voltage exceeding VCC may adversely affect the reliability of the chip. 14.3.10 LCD Drive Power Supply Voltages There are six LCD drive power supply voltage valuesV1 to V5, and VSS. V1 is the highest voltage, and VSS the lowest. As shown in figure 14.11, the common waveforms are formed from a combination of V1, V2, V5, and VSS, while the segment waveforms are formed from a combination of V1, V3, V4, and VSS. V1 and VSS are shared by both common and segment waveforms, but the intermediate voltages are different. In figure 14.11, the waveforms of outputs SEG1 to SEG40 differ according to the display data. In this example, LCD panel lines for which COM1 is connected are illuminated, and all other dots are not illuminated. Rev.3.00 Jul. 19, 2007 page 397 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 1 frame V1 V2 V3 COM1 V4 V5 VSS V1 V2 COM2 V3 V4 V5 VSS V1 V2 V3 COM16 V4 V5 VSS Line selection period SEG1 V1 V2 V3 V4 V5 VSS V1 V2 V3 SEG40 V4 V5 VSS Selected Not selected Figure 14.11 LCD Drive Power Supply Waveforms (1/16 Duty) Rev.3.00 Jul. 19, 2007 page 398 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.11 LCD Voltage Generation Circuit When Using Internal Power Supply and Built-In Bleeder Resistances The LCD controller includes bleeder resistances that generate levels V1 to V5. For the LCD drive power supply, drive can be performed using the internal power supply and VCC, or using an external supply. When the internal power supply is used, and the built-in bleeder resistances are employed, bits LPS1 and LPS0 in control register 2 (LR1) should both be set to 1. If the capacitance of the LCD panel to be driven is large, capacitors of around 0.1 to 0.5 F should be inserted between V1OUT to V5OUT and VSS to provide stabilization. VCC ON V1OUT R V2OUT R V3OUT R ON V4 R ON V5 R VSS ON VSS COM1 to COM16 ON V3 Control circuit ON V2 SEG1 to SEG40 LPS1 = 1 LPS0 = 1 V1 V4OUT V5OUT + 0.1 to 0.5 F + + + + VSS Note: When using 1/4 bias, short V3OUT and V4OUT. Figure 14.12 When Using Internal Power Supply and Built-In Bleeder Resistances (1/5 Bias) Rev.3.00 Jul. 19, 2007 page 399 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) When Using External Power Supply and Built-In Bleeder Resistances When an external power supply is supplied from V1OUT and the built-in bleeder resistances are used, clear LPS1 to 0 and set LPS0 to 1 in control register 2 (LR1), and make the connections shown in figure 14.13. The power supply applied to V1OUT must not exceed VCC. If the capacitance of the LCD panel to be driven is large, capacitors of around 0.1 to 0.5 F should be inserted between V1OUT to V5OUT and VSS to provide stabilization. External power supply V1OUT R V2OUT R V3OUT R ON ON V3 Control circuit V4 COM1 to COM16 V5 R VSS ON VSS ON V2 SEG1 to SEG40 VCC OFF LPS1 = 0 LPS0 = 1 V1 V4OUT V5OUT + 0.1 to 0.5 F + + + R ON VSS Notes: 1. When using 1/5 bias, do not short V3OUT and V4OUT. 2. Set VSS V1OUT VCC. Figure 14.13 When Using External Power Supply and Built-In Bleeder Circuit (1/4 Bias) Rev.3.00 Jul. 19, 2007 page 400 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) When Using External Power Supply and Bleeder Resistances If the drive capability of the built-in bleeder resistance is insufficient for the size of the LCD panel, the V1 to V5 levels can be supplied from external bleeder resistances. In this case, clear the LPS1 and LPS0 bits in control register 2 (LR1) to 0, and make the connections shown in figure 14.14. VCC OFF V1OUT Rx V2OUT Rx V3OUT Rx V4OUT Rx V5OUT Rx VSS OFF VSS OFF V5 OFF OFF V3 Control circuit V4 COM1 to COM16 OFF V2 SEG1 to SEG40 External power supply LPS1 = 0 LPS0 = 0 V1 VSS Notes: 1. When using 1/4 bias, short V3OUT and V4OUT. 2. Set VSS Vin VCC (Vin: V1OUT to V5OUT). 3. A value of around 5 k to 25 k is recommended for external power supply division resistances Rx. Figure 14.14 When Using External Power Supply and External Bleeder Circuit (1/5 Bias) Rev.3.00 Jul. 19, 2007 page 401 of 532 REJ09B0397-0300 14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.12 LCD Drive Bias Selection Circuit The ideal bias value that gives the best contrast is calculated using the equation shown below. If drive is performed at a bias value lower than the optimum, contrast will deteriorate, but the LCD drive voltage (the potential difference between V1 and VSS) can be kept low. If the output voltage falls and the LCD display becomes faint as batteries wear out, for instance, the display can be made clearer by decreasing the LCD drive bias. Optimum bias value for 1/N duty drive = 1 N+1 Notes: 1. When using 1/5 bias, leave the V3OUT and V4OUT pins open. 2. When using 1/4 bias, short the V3OUT and V4OUT pins. Rev.3.00 Jul. 19, 2007 page 402 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) Section 15 Electrical Characteristics (H8/3857 Group) 15.1 H8/3855, H8/3856, and H8/3857 Absolute Maximum Ratings (Standard Specifications) Table 15.1 shows the absolute maximum ratings. Table 15.1 Absolute Maximum Ratings Item Power supply voltage Analog power supply voltage LCD power supply voltage Programming voltage (FWE) Input voltage Except port B and LCD power supply Port B LCD power supply Operating temperature Storage temperature Caution: Symbol VCC AVCC VLCD Vin Vin AVin Vin Topr Tstg Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to +8.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to VLCD +0.3 -20 to +75 -55 to +125 Unit V V V V V V V C C *3 *4 *1 *2 Notes Notes: 1. 2. 3. 4. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. A voltage not lower than VCC must be applied as LCD power supply voltage VLCD. 12 V must not be applied to the FWE pin, as this will permanently damage the device. When the built-in op-amps are not used, and the LCD drive voltages are supplied directly from an external source, this applies to V1OUT, V2OUT, V3OUT, V4OUT, and V5OUT. The operating temperature range when programming/erasing flash memory is: Ta = 0C to +75C. Rev.3.00 Jul. 19, 2007 page 403 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) 15.2 H8/3855, H8/3856, and H8/3857 Electrical Characteristics (Standard Specifications) Power Supply Voltage and Operating Range 15.2.1 The power supply voltage and operating range of the H8/3855, H8/3856, and H8/3857 are indicated by the shaded region in the figures below. (1) Power Supply Voltage vs. Oscillator Frequency Range 10.0 32.768 fOSC (MHz) 5.0 2.0 3.0 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode fW (kHz) 3.0 * All operating modes 4.0 5.5 VCC (V) Rev.3.00 Jul. 19, 2007 page 404 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) (2) Power Supply Voltage vs. Operating Frequency Range 5.0 (MHz) 2.5 1.0 0.5 3.0 4.0 SUB (kHz) 19.200 16.384 * }* 5.5 VCC (V) * Active mode (high speed) * Sleep mode (except CPU) 9.600 8.192 4.800 4.096 3.0 4.0 * * 5.5 VCC (V) * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) 625.0 (kHz) 500.0 312.5 62.5 3.0 4.0 5.5 VCC (V) * Active mode (medium speed) Note: * In case of external clock only (3) Analog Power Supply Voltage vs. A/D Converter Operating Range 5.0 625.0 (MHz) 2.5 (kHz) 4.0 5.5 AVCC (V) 500.0 312.5 0.5 3.0 62.5 3.0 4.0 5.5 AVCC (V) * Active mode (medium speed) * Active mode (high speed) * Sleep mode (except CPU) Rev.3.00 Jul. 19, 2007 page 405 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) 15.2.2 DC Characteristics Table 15.2 shows the DC characteristics of the H8/3855, H8/3856, and H8/3857. Table 15.2 DC Characteristics of H8/3855, H8/3856, and H8/3857 (1) VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C*4, including subactive mode, unless otherwise specified. Values Item Input high voltage Symbol Applicable Pins VIH Test Conditions Min Typ Max Unit Notes VCC = 4.0 V to 5.5 V 0.8 VCC RES, WKP0 to WKP7, IRQ0 to IRQ4, TMIB, TMIC, TMIF, TEST2, FWE, 0.9 VCC SCK1, SCK3, ADTRG UD, SI1, RXD VCC = 4.0 V to 5.5 V 0.7 VCC 0.8 VCC OSC1 VCC +0.3 V VCC +0.3 VCC +0.3 V VCC +0.3 VCC +0.3 V VCC +0.3 VCC +0.3 V VCC +0.3 V VCC +0.3 VCC = 4.0 V to 5.5 V VCC -0.5 VCC -0.3 VCC -0.3 VCC = 4.0 V to 5.5 V 0.7 VCC 0.8 VCC X1 P10 to P17, P20 to P27, P30 to P37, P40 to P43, P50 to P57 PB0 to PB7 VCC = 4.0 V to 5.5 V 0.7 VCC 0.8 VCC AVCC +0.3 V AVCC +0.3 0.2 VCC V Input low voltage VIL VCC = 4.0 V to 5.5 V -0.3 RES, WKP0 to WKP7, IRQ0 to IRQ4, TMIB, TMIC, TMIF, TEST2, FWE, -0.3 SCK1, SCK3, ADTRG UD, SI1, RXD VCC = 4.0 V to 5.5 V -0.3 -0.3 OSC1 VCC = 4.0 V to 5.5 V -0.3 -0.3 0.1 VCC 0.3 VCC 0.2 VCC 0.5 0.3 V V Rev.3.00 Jul. 19, 2007 page 406 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) Values Item Input low voltage Symbol Applicable Pins VIL X1 P10 to P17, P20 to P27, P30 to P37, P40 to P43, P50 to P57, PB0 to PB7 VOH P10 to P17, P20 to P27, P30 to P37, P40 to P42, P50 to P57 P10 to P17, P40 to P42, P50 to P57 P20 to P27, P30 to P37 Test Conditions Min -0.3 VCC = 4.0 V to 5.5 V -0.3 Typ Max 0.3 0.3 VCC Unit Notes V V -0.3 0.2 VCC Output high voltage VCC = 4.0 V to 5.5 V VCC -1.0 -IOH = 1.0 mA VCC = 4.0 V to 5.5 V VCC -0.5 -IOH = 0.5 mA -IOH = 0.1 mA VCC -0.5 VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA VCC = 4.0 V to 5.5 V IOL = 10 mA VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA 0.6 0.5 1.5 0.6 0.5 1.0 V Output low voltage VOL V V Input/output IIL leakage current RES, TEST2, FWE, Vin = 0.5 V to OSC1, VCC - 0.5 V P10 to P17, P20 to P27, P30 to P37, P40 to P43, P50 to P57 PB0 to PB7 Vin = 0.5 V to AVCC - 0.5 V VCC = 5 V, Vin = 0 V VCC = 3.3 V, Vin= 0 V A 50.0 100 10.0 1.0 300.0 15.0 15.0 A A A pF mA * 2 * 1 Pull-up MOS -Ip current P10 to P17, P30 to P37, P50 to P57 Reference values Input Cin capacitance Active mode IOPE1 current dissipation IOPE2 All input pins except f = 1 MHz, Vin = 0 V, power supply pins Ta = 25C VCC Active mode (high speed) VCC = 5 V, fOSC = 10 MHz Active mode (medium speed) VCC = 5 V, fOSC = 10 MHz VCC 2.0 3.5 mA * 2 * 1 Rev.3.00 Jul. 19, 2007 page 407 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) Values Item Symbol Applicable Pins VCC Test Conditions VCC = 5 V, fOSC = 10 MHz VCC = 3.3 V, LCD on, (with 2X step-up) 32-kHz crystal oscillator used (SUB= W/2) VCC = 3.3 V, LCD on, (with 2X step-up) 32-kHz crystal oscillator used (SUB= W/8) Min Typ 4.0 Max 7.0 Unit Notes mA * 2 * * 2 * 1 1 Sleep mode ISLEEP current dissipation ISUB Subactive mode current dissipation VCC 70 150 A 65 A * 2 * Reference values * 2 * Reference values * 2 * 1 1 1 VCC = 3.3 V, LCD not used, 32kHz crystal oscillator used (SUB= W/2) ISUBSP Subsleep mode current dissipation VCC VCC = 3.3 V, LCD on, (with 2X step-up) 32-kHz crystal oscillator used (SUB= W/2) VCC = 3.3 V, LCD on, (with 2X step-up) 32-kHz crystal oscillator used VCC = 3.3 V, LCD not used, 32-kHz crystal oscillator used ISTBY Standby mode current dissipation IFLASH Program/ erase current dissipation RAM data retaining voltage VRAM VCC 32-kHz crystal oscillator not used 0C Ta 70C fOSC = 12 MHz 20 A 65 130 A Watch mode IWATCH current dissipation VCC 60 90.0 A * 2 * 1 7.0 15.0 A * 2 * 1 5.0 A * 2 * * 2 * 3 * * 2 * 1 1 1 VCC 16 22 mA VCC 2.0 V Rev.3.00 Jul. 19, 2007 page 408 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) Notes: 1. Pin states during current measurement Mode Internal State Pins VCC VCC VCC LCD Power Supply VLCD = 6.0 V VLCD = 6.0 V VLCD = 6.0 V (When LCD is not used, VLCD = VCC) VLCD = 6.0 V VLCD = 6.0 V (When LCD is not used, VLCD = VCC) VLCD = VCC VLCD = VCC System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC System clock oscillator: Crystal Subclock oscillator: Crystal Oscillator Pins System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC Active mode (high Operates and medium speed) Sleep mode Subactive mode Only timer operates Operates Subsleep mode Watch mode Only timer operates, CPU stops Only time-base clock operates, CPU stops VCC VCC Standby mode Programming/ 3 erasing* CPU and timers all stop VCC Operates VCC 2. Excludes current in pull-up MOS transistors and output buffers. 3. Applies to F-ZTAT version only. 4. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 409 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) Table 15.3 DC Characteristics of H8/3855, H8/3856, and H8/3857 (2) VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C*2, including subactive mode, unless otherwise specified. Values Item Allowable output low current (per pin) Symbol Applicable Pins IOL Output pins except in ports 2 and 3 Ports 2 and 3 All output pins Allowable IOL output low current (total) Output pins except in ports 2 and 3 Ports 2 and 3 All output pins Allowable output high current (per pin) -IOH All output pins VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Test Conditions VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Min All output pins VCC = 4.0 V to 5.5 V Typ Max 2.0 10.0 0.5 20.0 80.0 20.0 2.0 0.2 10.0 8.0 mA * 1 Unit mA Notes * 1 mA * 1 mA * 1 -IOH Allowable output high current (total) Notes: 1. Excludes LCD output pins. 2. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 410 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) 15.2.3 AC Characteristics Table 15.4 shows the control signal timing, and tables 15.5 and 15.6 show the serial interface timing, of the H8/3855, H8/3856, and H8/3857. Table 15.4 Control Signal Timing of H8/3855, H8/3856, and H8/3857 VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C*3, including subactive mode, unless otherwise specified. Applicable Symbol Pins OSC1, OSC2 Values Test Conditions Min Typ Max 10.0 5.0 1000.0 ns 1000.0 16 tOSC kHz s tW tcyc tsubcyc ms * 2 Item Reference Unit Figure MHz 1 System clock fOSC oscillation frequency OSC clock (OSC) cycle time System clock () cycle time tOSC tcyc VCC = 4.0 V to 5.5 V 2.0 2.0 VCC = 4.0 V to 5.5 V 100.0 200.0 2 2 2 OSC1, OSC2 * Figure 15.1 * 1 2000.0 ns Subclock oscillation fW frequency Watch clock (W) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal oscillator) Oscillation stabilization time External clock high width External clock low width External clock rise time External clock fall time trc tW tsubcyc X1, X2 X1, X2 32.768 30.5 8 15.0 20.0 15.0 20.0 OSC1, OSC2 VCC = 4.0 V to 5.5 V 40.0 60.0 trc tCPH tCPL tCPr tCPf X1, X2 OSC1 OSC1 OSC1 OSC1 2 VCC = 4.0 V to 5.5 V 40.0 80.0 VCC = 4.0 V to 5.5 V 40.0 80.0 VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V s ns Figure 15.1 ns Figure 15.1 ns Figure 15.1 ns Figure 15.1 Rev.3.00 Jul. 19, 2007 page 411 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) Applicable Symbol Pins tXH tXL tXr tXf tREL tIH X1 X1 X1 X1 RES IRQ0 to IRQ4, WKP0 to WKP7, ADTRG, TMIB, TMIC, TMIF IRQ0 to IRQ4, WKP0 to WKP7, ADTRG, TMIB, TMIC, TMIF UD Values Test Conditions Min 0.4/fx 0.4/fx 10 2 Typ Max 100.0 100.0 Reference Unit Figure s s ns ns tcyc Figure 15.2 Figure 15.2 Figure 15.2 Figure 15.2 Figure 15.3 Item External subclock high width External subclock low width External subclock rise time External subclock fall time RES pin low width Input pin high width tcyc Figure 15.4 tsubcyc Input pin low width tIL 2 tcyc Figure 15.4 tsubcyc UD pin minimum transition width tUDH tUDL 4 tcyc Figure 15.5 tsubcyc Notes: 1. A frequency between 1 MHz and 10 MHz is required when an external clock is input. 2. Selected with bits SA1 and SA0 in system control register 2 (SYSCR2). 3. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 412 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) Table 15.5 Serial Interface (SCI1) Timing of H8/3855, H8/3856, and H8/3857 VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C*, unless otherwise specified. Applicable Symbol Pins tScyc tSCKH tSCKL tSCKr tSCKf tSOD tSIS tSIH SCK1 SCK1 SCK1 SCK1 SCK1 SO1 SI1 SI1 VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Values Test Conditions Min 4 0.4 0.4 200.0 400.0 200.0 400.0 Typ Max 60.0 80.0 60.0 80.0 200.0 350.0 ns Figure 15.6 ns Figure 15.6 ns Figure 15.6 ns Figure 15.6 Reference Unit Figure tcyc tScyc tScyc ns Figure 15.6 Figure 15.6 Figure 15.6 Figure 15.6 Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Note: * The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 413 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) Table 15.6 Serial Interface (SCI3) Timing of H8/3855, H8/3856, and H8/3857 VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C*, unless otherwise specified. Values Item Symbol Test Conditions Min 4 6 0.4 VCC = 4.0 V to 5.5 V tRXS tRXH Typ Max 0.6 1 1 ns Figure 15.8 ns Figure 15.8 tScyc tcyc Figure 15.7 Figure 15.8 Unit tcyc Reference Figure Figure 15.7 Input clock Asynchronous tScyc cycle Synchronous Input clock pulse width Transmit data delay time (synchronous mode) Receive data setup time (synchronous mode) Receive data hold time (synchronous mode) Note: * tSCKW tTXD VCC = 4.0 V to 5.5 V 200.0 400.0 VCC = 4.0 V to 5.5 V 200.0 400.0 The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 414 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) 15.2.4 A/D Converter Characteristics Table 15.7 shows the A/D converter characteristics of the H8/3855, H8/3856, and H8/3857. Table 15.7 A/D Converter Characteristics of H8/3855, H8/3856, and H8/3857 VCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C*4, unless otherwise specified. Applicable Item Symbol Pins AVCC AN0 to AN7 AVCC AVCC AVCC = 5.0 V AVCC = 5.0 V Analog power supply AVCC voltage Analog input voltage AVIN Analog power supply AIOPE current AISTOP1 Test Conditions Min 3.0 AVSS -0.3 Values Typ 300 Max 5.5 Reference Unit Figure V * 1 AVCC +0.3 V 1.5 mA A * Reference value * 3 2 AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Non-linearity error Quantization error Absolute accuracy Conversion time CAIN RAIN AVCC AN0 to AN7 12.4 5.0 30.0 5.0 8 2.0 0.5 2.5 124 A pF k Bit LSB LSB LSB s Notes: 1. Set AVCC VCC, and set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 415 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) 15.2.5 LCD Characteristics Table 15.8 shows the LCD characteristics, and table 15.9 shows the step-up circuit characteristics, of the H8/3855, H8/3856, and H8/3857. Table 15.8 LCD Characteristics of H8/3855, H8/3856, and H8/3857 VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C*4, including subactive mode, unless otherwise specified. Values Item Common driver on-resistance Segment driver on-resistance LCD power supply current LCD power supply voltage Symbol Applicable Pins Test Conditions Min RCOM RSEG IEE VLCD COM1 to COM32 Id = 0.05 mA, VLCD = 4 V SEG1 to SEG64 Id = 0.05 mA, VLCD = 4 V VLCD VLCD VLCD = 5.5 V, fx = 32.768 kHz VCC Typ 6 6 20 Max Unit Notes 20 20 40 7.0 k k A V *1 *1 *2 *3 Notes: 1. Applies to the resistance (RCOM) between the V1OUT, V2OUT, V5OUT, and VSS pins and the common signal pins (COM1 to COM32), and the resistance (RSEG) between the V1OUT, V3OUT, V4OUT, and VSS pins and the segment signal pins (SEG1 to SEG64), when Id is flowing in the pins. 2. This is the current when the built-in op-amps are operating and display is halted (all driver outputs are at the VSS level). 3. Specifies the voltage range in which the COM/SEG pin output voltages are within the LCD reference voltage values (V1, V2, V3, V4, V5, and VSS) 0.15 V in the unloaded state. A voltage not lower than VCC must be applied to VLCD. 4. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 416 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) Table 15.9 Step-Up Circuit Characteristics of H8/3855, H8/3856, and H8/3857 VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C*2, including subactive mode, unless otherwise specified. Values Applicable Symbol Pins Test Conditions Min Typ Max Unit Notes VLOUT VCC = Vci = 3.0 V, IO = 0.03 mA, C = 1 F, X1 = 32 kHz, Ta = 25C VCC = 3.0 V, Vci = 2.0 V, IO = 0.03 mA, C = 1 F, X1 = 32 kHz, Ta = 25C Vci VCC 5.96 V Figure 15.9 Reference values Item 2X step-up output VUP2 voltage 3X step-up output VUP3 voltage VLOUT 5.90 V Figure 15.9 Reference values Step-up circuit Vci reference voltage Vci 1.6 3.5 V *1 Notes: 1. As VCC VLOUT 7.0 V, with 2X step-up VCC/2 Vci 3.5 V, and with 3X step-up VCC/3 Vci 2.33 V. A voltage not exceeding VCC should be input to Vci. If this condition is not observed, there is a risk of permanent damage to the device. 2. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 417 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) 15.2.6 Flash Memory Characteristics Table 15.10 shows the flash memory characteristics. Table 15.10 Flash Memory Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = 0C to +75C (program/erase operating temperature range) Item Programming time* * * Erase time* * * Rewrite times Programming Wait time after SWE bit setting* Wait time after PSU bit setting* Wait time after P bit setting* * Wait time after P bit clearing* 14 1 1 1 1 135 124 Symbol tP tE NWEC x y z 1 1 Min 10 50 10 10 4 2 4 10 200 10 10 20 2 5 Typ Max Unit 10 100 200 300 100 200 5 60 ms/32 bytes ms/block Times s s s s s s s s s s ms s s s s s Times Test Conditions Wait time after PSU bit clearing* Wait time after PV bit setting* 1 Wait time after H'FF dummy write* Wait time after PV bit clearing* Maximum number of writes* * Erasing 14 1 N x y z 1 1000 Times Wait time after SWE bit setting* Wait time after ESU bit setting* Wait time after E bit setting* * Wait time after E bit clearing* 15 1 1 Wait time after ESU bit clearing* Wait time after EV bit setting* 1 1 Wait time after H'FF dummy write* Wait time after EV bit clearing* Maximum number of erases* * 1 N 15 Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 32 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time (tP(max) = Wait time after P bit setting (z) x maximum number of writes (N)) 5. Maximum erase time (tE(max) = Wait time after E bit setting (z) x maximum number of erases (N)) Rev.3.00 Jul. 19, 2007 page 418 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) 15.3 Operation Timing Figures 15.1 to 15.8 show timing diagrams. tOSC OSC1 VIH VIL tCPH tCPr tCPL tCPf Figure 15.1 System Clock Input Timing X1 VIH VIL tXH tXr tXL tXf Figure 15.2 Subclock Input Timing RES VIL tREL Figure 15.3 RES Pin Low Width Timing IRQ0 to IRQ4, WKP0 to WKP7, ADTRG, TMIB, TMIC, TMIF VIH VIL tIL tIH Figure 15.4 Input Timing UD VIL tUDL tUDH VIH Figure 15.5 UD Pin Minimum Transition Width Timing Rev.3.00 Jul. 19, 2007 page 419 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) tScyc SCK1 VIH or VOH* VIL or VOL* tSCKL tSCKf tSOD SO1 VOH* VOL* tSIS tSIH SI1 Note: * Output timing reference levels Output high Output low VOH = 2.0 V VOL = 0.8 V tSCKH tSCKr Load conditions are shown in figure 15.10. Figure 15.6 SCI1 Input/Output Timing tSCKW SCK3 tScyc Figure 15.7 SCK3 Input Clock Timing Rev.3.00 Jul. 19, 2007 page 420 of 532 REJ09B0397-0300 15. Electrical Characteristics (H8/3857 Group) tScyc SCK3 VIH or VOH* VIL or VOL* tTXD TXD (transmit data) VOH* VOL* tRXS RXD (receive data) tRXH Note: * Output timing reference levels Output high Output low VOH = 2.0 V VOL = 0.8 V Load conditions are shown in figure 15.10. Figure 15.8 SCI3 Input/Output Timing in Synchronous Mode (2X step-up) IO 1 F + + 1 F IO 1 F + (3X step-up) 1 F 1 F + + 2.0 V VSS VLCD VLOUT C1+ C1- C2+ C2- VCi VSS 3.0 V 3.0 V VSS VCC VCC Figure 15.9 Step-Up Circuit Characteristics Test Circuits Rev.3.00 Jul. 19, 2007 page 421 of 532 REJ09B0397-0300 VSS VLCD VLOUT C1+ C1- C2+ C2- VCi 15. Electrical Characteristics (H8/3857 Group) 15.4 Output Load Circuit VCC 2.4 k LSI Chip Output pin 30 pF 12 k Figure 15.10 Output Load Conditions 15.5 Usage Note Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns. If the F-ZTAT version is used to carry out system evaluation and testing, therefore, when switching to the mask ROM version the same evaluation and testing procedures should also be conducted on the mask ROM version. Rev.3.00 Jul. 19, 2007 page 422 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) Section 16 Electrical Characteristics (H8/3854 Group) 16.1 H8/3852, H8/3853, and H8/3854 Absolute Maximum Ratings (Standard Specifications) Table 16.1 shows the absolute maximum ratings. Table 16.1 Absolute Maximum Ratings Item Power supply voltage Programming voltage (FWE) Input voltage Except LCD power supply LCD power supply Operating temperature Storage temperature Caution: Symbol VCC Vin Vin Vin Topr Tstg Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -20 to +75 -55 to +125 Unit V V V V C C *2 *3 *1 Notes Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. Notes: 1. 12 V must not be applied to the FWE pin, as this will permanently damage the device. 2. When the internal power supply and internal bleeder resistances are not used, and the LCD drive voltages are supplied directly from an external source, this applies to V1OUT, V2OUT, V3OUT, V4OUT, and V5OUT. 3. The operating temperature range when programming/erasing flash memory is: Ta = 0C to +75C. Rev.3.00 Jul. 19, 2007 page 423 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) 16.2 H8/3852, H8/3853, and H8/3854 Electrical Characteristics (Standard Specifications) Power Supply Voltage and Operating Range 16.2.1 The power supply voltage and operating range of the H8/3852, H8/3853, and H8/3854 are indicated by the shaded region in the figures below. (1) Power Supply Voltage vs. Oscillator Frequency Range 10.0 32.768 fOSC (MHz) 5.0 2.0 2.7* 3.0 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode fW (kHz) 2.7* 3.0 4.0 5.5 VCC (V) * Active mode (medium speed) Note: * The minimum VCC level of the H8/3854F is 3.0 V. Rev.3.00 Jul. 19, 2007 page 424 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) (2) Power Supply Voltage vs. Operating Frequency Range 5.0 (MHz) 2.5 1.0 0.5 2.7*2 3.0 4.0 SUB (kHz) 19.200 16.384 *1 } *1 5.5 VCC (V) * Active mode (high speed) * Sleep mode (except CPU) 9.600 8.192 4.800 4.096 2.7*2 3.0 4.0 *1 *1 5.5 VCC (V) * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) 625.0 (kHz) Notes: 1. In case of external clock only 2. The minimum VCC level of the H8/3854F is 3.0 V. 500.0 312.5 62.5 2.7 3.0 4.0 5.5 VCC (V) * Active mode (medium speed) (3) Power Supply Voltage vs. A/D Converter Operating Range 5.0 625.0 (MHz) 2.5 (kHz) 500.0 312.5 0.5 2.7* 3.0 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode 62.5 2.7 3.0 4.0 5.5 VCC (V) * Active mode (medium speed) Note: * The minimum VCC level of the H8/3854F is 3.0 V. Rev.3.00 Jul. 19, 2007 page 425 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) 16.2.2 DC Characteristics Table 16.2 shows the DC characteristics of the H8/3852, H8/3853, and H8/3854. Table 16.2 DC Characteristics of H8/3852, H8/3853, and H8/3854 (1) VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*4, including subactive mode, unless otherwise specified. Values Item Input high voltage Symbol Applicable Pins VIH RES, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, TMIB, TMIF, TEST2, FWE, SCK3, ADTRG RXD Test Conditions Min Typ Max Unit Notes VCC = 4.0 V to 5.5 V 0.8 VCC VCC +0.3 V 0.9 VCC VCC +0.3 VCC = 4.0 V to 5.5 V 0.7 VCC 0.8 VCC VCC +0.3 V VCC +0.3 VCC +0.3 V VCC +0.3 VCC +0.3 V VCC +0.3 V VCC +0.3 OSC1 VCC = 4.0 V to 5.5 V VCC -0.5 VCC -0.3 VCC -0.3 VCC = 4.0 V to 5.5 V 0.7 VCC 0.8 VCC X1 P10 to P12, P15, P17, P20 to P27, P40 to P43, P50 to P57, PB4 to PB7 Input low voltage VIL RES, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, TMIB, TMIF, TEST2, FWE, SCK3, ADTRG RXD VCC = 4.0 V to 5.5 V -0.3 0.2 VCC V -0.3 0.1 VCC VCC = 4.0 V to 5.5 V -0.3 -0.3 0.3 VCC 0.2 VCC 0.5 0.3 V OSC1 VCC = 4.0 V to 5.5 V -0.3 -0.3 V Rev.3.00 Jul. 19, 2007 page 426 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) Values Item Input low voltage Symbol Applicable Pins VIL X1 P10 to P12, P15, P17, P20 to P27, P40 to P43, P50 to P57, PB4 to PB7 VOH P10 to P12, P15, P17, P20 to P27, P40 to P42, P50 to P57 P10 to P12, P15, P17, P40 to P42, P50 to P57 P20 to P27 Test Conditions Min -0.3 VCC = 4.0 V to 5.5 V -0.3 Typ Max 0.3 0.3 VCC Unit Notes V V -0.3 0.2 VCC Output high voltage VCC = 4.0 V to 5.5 V VCC -1.0 -IOH = 1.0 mA VCC = 4.0 V to 5.5 V VCC -0.5 -IOH = 0.5 mA -IOH = 0.1 mA VCC -0.5 VCC = 4.0 V to 5.5 V IOL= 1.6 mA IOL= 0.4 mA 0.6 0.5 1.5 0.6 0.5 1.0 V Output low voltage VOL V VCC = 4.0 V to 5.5 V IOL= 10 mA VCC = 4.0 V to 5.5 V IOL= 1.6 mA IOL= 0.4 mA Input/output IIL leakage current RES, TEST2, FWE, OSC1, P10 to P12, P15, P17, P20 to P27, P40 to P43, P50 to P57, PB4 to PB7 P10 to P12, P15, P17, P50 to P57 Vin = 0.5 V to VCC - 0.5 V A Pull-up MOS -Ip current VCC = 5 V, Vin= 0 V VCC = 3.3 V, Vin = 0 V 50.0 100 300.0 15.0 A A pF Reference values Input Cin capacitance All input pins except f = 1 MHz, Vin = 0 V, power supply pins Ta = 25C Rev.3.00 Jul. 19, 2007 page 427 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) Values Item Symbol Applicable Pins VCC Test Conditions Active mode (high speed) VCC = 5 V, fOSC = 10 MHz A/D not used Active mode (high speed) VCC = 5 V, fOSC = 10 MHz A/D operating Active mode (medium speed) VCC = 5 V, fOSC = 10 MHz A/D not used VCC = 5 V, fOSC = 10 MHz A/D not used VCC = 5.0 V, LCD on, 32-kHz crystal oscillator used (SUB= W/2) VCC = 5.0 V, LCD on, 32-kHz crystal oscillator used (SUB= W/8) Min Typ 10.0 Max 15.0 Unit Notes mA * 2 * 1 Active mode IOPE1 current dissipation IOPE3 VCC 16.5 mA * 2 * 1 IOPE2 VCC 2.0 3.5 mA * 2 * 1 Sleep mode ISLEEP current dissipation Subactive ISUB mode current dissipation VCC 4.3 7.0 mA * 2 * * 2 * 5 * * 2 * 5 * Reference values * 2 * Reference values * 2 * 5 * * 2 * 5 * * 2 * 1 1 1 1 1 1 1 VCC 80 160 A 70 A VCC = 3.3 V, LCD not used, 32kHz crystal oscillator used (SUB= W/2) Subsleep ISUBSP mode current dissipation Watch mode IWATCH current dissipation VCC VCC = 5.0 V, LCD on, 32-kHz crystal oscillator used (SUB= W/2) VCC = 5.0 V, LCD on, 32-kHz crystal oscillator used VCC = 3.3 V, LCD not used, 32-kHz crystal oscillator used Standby ISTBY mode current dissipation VCC 32-kHz crystal oscillator not used 20 A 50 100 A VCC 40 80 A 7.0 15.0 A 5.0 A * 2 * 1 Rev.3.00 Jul. 19, 2007 page 428 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) Values Item Symbol Applicable Pins VCC Test Conditions 0C Ta 70C fOSC = 12 MHz Min Typ 16 Max 22 Unit Notes mA * 2 * 3 * * 2 * 1 1 IFLASH Program/ erase current dissipation RAM data retaining voltage VRAM VCC 2.0 V Notes: 1. Pin states during current measurement Mode Active mode (high and medium speed) Sleep mode Subactive mode Subsleep mode Watch mode Standby mode Programming/ 3 erasing* Internal State Operates Only timer operates Operates Only timer operates, CPU stops Only time-base clock operates, CPU stops CPU and timers all stop Operates Pins VCC VCC VCC VCC VCC VCC VCC System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC System clock oscillator: Crystal Subclock oscillator: Crystal Oscillator Pins System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC 2. Excludes current in pull-up MOS transistors and output buffers. 3. Applies to F-ZTAT version only. 4. The guaranteed temperature as an electrical characteristic for die type products is 75C. 5. When power is supplied to the built-in bleeder resistances from VCC (LPS0 = LPS1 = 1 in LR2). Rev.3.00 Jul. 19, 2007 page 429 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) Table 16.3 DC Characteristics of H8/3852, H8/3853, and H8/3854 (2) VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*2, including subactive mode, unless otherwise specified. Values Item Allowable output low current (per pin) Symbol Applicable Pins IOL Output pins except in port 2 Port 2 All output pins Allowable IOL output low current (total) Output pins except in port 2 Port 2 All output pins Allowable output high current (per pin) -IOH All output pins VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Test Conditions VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Min All output pins VCC = 4.0 V to 5.5 V Typ Max 2.0 10.0 0.5 20.0 80.0 20.0 2.0 0.2 10.0 8.0 mA * 1 Unit mA Notes * 1 mA * 1 mA * 1 -IOH Allowable output high current (total) Notes: 1. Excludes LCD output pins. 2. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 430 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) 16.2.3 AC Characteristics Table 16.4 shows the control signal timing, and table 16.5 shows the serial interface timing, of the H8/3852, H8/3853, and H8/3854. Table 16.4 Control Signal Timing of H8/3852, H8/3853, and H8/3854 VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*3, including subactive mode, unless otherwise specified. Applicable Symbol Pins OSC1, OSC2 Values Test Conditions Min Typ Max 10.0 5.0 1000.0 ns 1000.0 16 tOSC kHz s tW tcyc tsubcyc ms * 2 Item Reference Unit Figure MHz 1 System clock fOSC oscillation frequency OSC clock (OSC) cycle time System clock () cycle time tOSC tcyc VCC = 4.0 V to 5.5 V 2.0 2.0 VCC = 4.0 V to 5.5 V 100.0 200.0 2 2 2 OSC1, OSC2 * Figure 16.1 * 1 2000.0 ns Subclock oscillation fW frequency Watch clock (W) cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time (crystal oscillator) Oscillation stabilization time External clock high width External clock low width External clock rise time External clock fall time trc tW tsubcyc X1, X2 X1, X2 32.768 30.5 8 15.0 20.0 15.0 20.0 OSC1, OSC2 VCC = 4.0 V to 5.5 V 40.0 60.0 trc tCPH tCPL tCPr tCPf X1, X2 OSC1 OSC1 OSC1 OSC1 2 VCC = 4.0 V to 5.5 V 40.0 80.0 VCC = 4.0 V to 5.5 V 40.0 80.0 VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V s ns Figure 16.1 ns Figure 16.1 ns Figure 16.1 ns Figure 16.1 Rev.3.00 Jul. 19, 2007 page 431 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) Applicable Symbol Pins tXH tXL tXr tXf tREL tIH X1 X1 X1 X1 RES IRQ0, IRQ1, IRQ3, IRQ4, WKP0 to WKP7, ADTRG, TMIB, TMIF IRQ0, IRQ1, IRQ3, IRQ4, WKP0 to WKP7, ADTRG, TMIB, TMIF Values Test Conditions Min 0.4/fx 0.4/fx 10 2 Typ Max 100.0 100.0 Reference Unit Figure s s ns ns tcyc Figure 16.2 Figure 16.2 Figure 16.2 Figure 16.2 Figure 16.3 Item External subclock high width External subclock low width External subclock rise time External subclock fall time RES pin low width Input pin high width tcyc Figure 16.4 tsubcyc Input pin low width tIL 2 tcyc Figure 16.4 tsubcyc Notes: 1. A frequency between 1 MHz and 10 MHz is required when an external clock is input. 2. Selected with bits SA1 and SA0 in system control register 2 (SYSCR2). 3. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 432 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) Table 16.5 Serial Interface (SCI3) Timing of H8/3852, H8/3853, and H8/3854 VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*, unless otherwise specified. Values Item Symbol Test Conditions Min 4 6 0.4 VCC = 4.0 V to 5.5 V tRXS tRXH Typ Max 0.6 1 1 ns Figure 16.6 ns Figure 16.6 tScyc tcyc Figure 16.5 Figure 16.6 Unit tcyc Reference Figure Figure 16.5 Input clock Asynchronous tScyc cycle Synchronous Input clock pulse width Transmit data delay time (synchronous mode) Receive data setup time (synchronous mode) Receive data hold time (synchronous mode) tSCKW tTXD VCC = 4.0 V to 5.5 V 200.0 400.0 VCC = 4.0 V to 5.5 V 200.0 400.0 Note: * The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 433 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) 16.2.4 A/D Converter Characteristics Table 16.6 shows the A/D converter characteristics of the H8/3852, H8/3853, and H8/3854. Table 16.6 A/D Converter Characteristics of H8/3852, H8/3853, and H8/3854 VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*, unless otherwise specified. Applicable Item Symbol Pins AN4 to AN7 AN4 to AN7 Analog input voltage AVIN Analog input capacitance Allowable signal source impedance Resolution (data length) Non-linearity error Quantization error Absolute accuracy Conversion time CAIN RAIN Test Conditions Min VSS -0.3 12.4 Values Typ Max VCC +0.3 30.0 5.0 8 2.0 0.5 2.5 124 Reference Unit Figure V pF k Bit LSB LSB LSB s Note: * The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 434 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) 16.2.5 LCD Characteristics Table 16.7 shows the LCD characteristics of the H8/3852, H8/3853, and H8/3854. Table 16.7 LCD Characteristics of H8/3852, H8/3853, and H8/3854 VCC = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, VCC = 3.0 V to 5.5 V of H8/3854F, VSS = 0.0 V, Ta = -20C to +75C*2, including subactive mode, unless otherwise specified. Values Item Common driver on-resistance Segment driver on-resistance LCD power supply bleeder resistance Symbol Applicable Pins Test Conditions Min RCOM RSEG RLCD COM1 to COM16 Id = 0.05 mA, VCC = 4 V SEG1 to SEG40 Id = 0.05 mA, VCC = 4 V VCC = 5.0 V, fx = 32.768 kHz 200 Typ 6 6 400 Max Unit Notes 20 20 700 k k k *1 *1 Notes: 1. Applies to the resistance (RCOM) between the V1OUT, V2OUT, V5OUT, and VSS pins and the common signal pins (COM1 to COM16), and the resistance (RSEG) between the V1OUT, V3OUT, V4OUT, and VSS pins and the segment signal pins (SEG1 to SEG40), when Id is flowing in the pins. The voltage applied to V1OUT through V5OUT must not exceed VCC. 2. The guaranteed temperature as an electrical characteristic for die type products is 75C. Rev.3.00 Jul. 19, 2007 page 435 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) 16.2.6 Flash Memory Characteristics Table 16.8 shows the flash memory characteristics. Table 16.8 Flash Memory Characteristics Conditions: VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Ta = 0C to +75C (program/erase operating temperature range) Item Programming time* * * Erase time* * * Rewrite times Programming Wait time after SWE bit setting* Wait time after PSU bit setting* Wait time after P bit setting* * Wait time after P bit clearing* 14 1 1 1 1 135 124 Symbol tP tE NWEC x y z 1 1 Min 10 50 10 10 4 2 4 10 200 10 10 20 2 5 Typ Max Unit 10 100 200 300 100 200 5 60 ms/32 bytes ms/block Times s s s s s s s s s s ms s s s s s Times Test Conditions Wait time after PSU bit clearing* Wait time after PV bit setting* 1 Wait time after H'FF dummy write* Wait time after PV bit clearing* Maximum number of writes* * Erasing 14 1 N x y z 1 1000 Times Wait time after SWE bit setting* Wait time after ESU bit setting* Wait time after E bit setting* * Wait time after E bit clearing* 15 1 1 Wait time after ESU bit clearing* Wait time after EV bit setting* 1 1 Wait time after H'FF dummy write* Wait time after EV bit clearing* Maximum number of erases* * 1 N 15 Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 32 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time (tP(max) = Wait time after P bit setting (z) x maximum number of writes (N)) 5. Maximum erase time (tE(max) = Wait time after E bit setting (z) x maximum number of erases (N)) Rev.3.00 Jul. 19, 2007 page 436 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) 16.3 Operation Timing Figures 16.1 to 16.6 show timing diagrams. tOSC OSC1 VIH VIL tCPH tCPr tCPL tCPf Figure 16.1 System Clock Input Timing X1 VIH VIL tXH tXr tXL tXf Figure 16.2 Subclock Input Timing RES VIL tREL Figure 16.3 RES Pin Low Width Timing IRQ0, IRQ1, IRQ3, IRQ4, WKP0 to WKP7, ADTRG, TMIB, TMIF VIH VIL tIL tIH Figure 16.4 Input Timing tSCKW SCK3 tScyc Figure 16.5 SCK3 Input Clock Timing Rev.3.00 Jul. 19, 2007 page 437 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) tScyc SCK3 VIH or VOH* VIL or VOL* tTXD TXD (transmit data) VOH* VOL* tRXS RXD (receive data) tRXH Note: * Output timing reference levels Output high Output low VOH = 2.0 V VOL = 0.8 V Load conditions are shown in figure 16.7. Figure 16.6 SCK3 Input/Output Timing in Synchronous Mode 16.4 Output Load Circuit VCC 2.4 k LSI Chip output pin 30 pF 12 k Figure 16.7 Output Load Conditions Rev.3.00 Jul. 19, 2007 page 438 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) 16.5 Usage Note Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns. If the F-ZTAT version is used to carry out system evaluation and testing, therefore, when switching to the mask ROM version the same evaluation and testing procedures should also be conducted on the mask ROM version. Rev.3.00 Jul. 19, 2007 page 439 of 532 REJ09B0397-0300 16. Electrical Characteristics (H8/3854 Group) Rev.3.00 Jul. 19, 2007 page 440 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Appendix A CPU Instruction Set A.1 Instructions Operation Notation Symbol Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx: 3/8/16 d: 8/16 @aa: 8/16 + - x / -- Description General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move Logical complement Rev.3.00 Jul. 19, 2007 page 441 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Condition Code Notation Symbol Description Modified according to the instruction result * 0 Not fixed (value not guaranteed) Always cleared to 0 Not affected by the instruction execution result Rev.3.00 Jul. 19, 2007 page 442 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Table A.1 Instruction Set Addressing Mode/ Instruction Length (Bytes) Operand Size @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 Condition Code No. of States #xx: 8/16 MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd W Rs16 Rd16 W @Rs16 Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP Implied @@aa Mnemonic Operation I HNZVC @Rn Rn 2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 02 02 04 06 06 04 06 04 06 06 04 06 04 02 04 06 06 06 04 06 06 06 06 MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd Rev.3.00 Jul. 19, 2007 page 443 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States Operand Size @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 PUSH Rs ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd MULXU.B Rs, Rd W SP-2 SP Rs16 @SP B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8 +C Rd8 B Rd8+Rs8 +C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8 -C Rd8 B Rd8-Rs8 -C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd Rd B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 B Rd8 x Rs8 Rd16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Implied @@aa Mnemonic Operation I HNZVC @Rn Rn 2 (1) (2) (2) 06 2 2 2 2 2 2 2 * (1) (2) (2) 2 * (3) 2 2 2 2 2 2 2 * (1) 2 *2 2 2 2 2 14 Rev.3.00 Jul. 19, 2007 page 444 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Operand Size @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 Condition Code No. of States #xx: 8/16 DIVXU.B Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd SHAL.B Rd B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd Rd B 2 2 2 Implied @@aa Mnemonic Operation I HNZVC @Rn Rn 2 (5) (6) 14 02 02 02 02 02 02 02 2 2 2 2 2 C b7 b0 0 2 SHAR.B Rd B C b7 b0 0 b7 b0 C b7 b0 2 0 2 SHLL.B Rd B C 2 0 2 SHLR.B Rd B 0 2 0 0 2 ROTXL.B Rd B C b7 b0 2 0 2 ROTXR.B Rd B 2 0 2 b7 ROTL.B Rd B b0 C 2 0 2 C b7 b0 C b7 b0 ROTR.B Rd B 2 0 2 Rev.3.00 Jul. 19, 2007 page 445 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States Operand Size @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z Implied @@aa Mnemonic Operation I HNZVC @Rn Rn 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 Rev.3.00 Jul. 19, 2007 page 446 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Operand Size @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 Condition Code No. of States #xx: 8/16 BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C Implied @@aa Mnemonic Operation I HNZVC @Rn Rn 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 2 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 Rev.3.00 Jul. 19, 2007 page 447 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States Operand Size @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8 B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C PC PC+d:8 PC PC+2 If condition is true then PC PC+d:8 else next; PC Rn16 PC aa:16 PC @aa:8 SP-2 SP PC @SP PC PC+d:8 SP-2 SP PC @SP PC Rn16 SP-2 SP PC @SP PC aa:16 CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1 Implied @@aa Mnemonic Operation @Rn Branching Condition I HNZVC Rn 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 2 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 8 6 JSR @Rn 2 6 JSR @aa:16 4 8 Rev.3.00 Jul. 19, 2007 page 448 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Operand Size @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 Condition Code No. of States #xx: 8/16 JSR @@aa:8 SP-2 SP PC @SP PC @aa:8 PC @SP SP+2 SP CCR @SP SP+2 SP PC @SP SP+2 SP Transit to power-down state B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR PC PC+2 if R4L 0 Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L = 0 else next; 2 2 2 2 2 2 Implied @@aa Mnemonic Operation I HNZVC @Rn Rn 2 8 RTS RTE 2 8 2 10 SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP EEPMOV 2 2 2 2 2 2 2 2 2 2 4 (4) Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) The number of states required for execution is 4n + 9 (n = value of R4L). (5) Set to 1 if the divisor is negative; otherwise cleared to 0. (6) Set to 1 if the divisor is zero; otherwise cleared to 0. Rev.3.00 Jul. 19, 2007 page 449 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set A.2 Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. Rev.3.00 Jul. 19, 2007 page 450 of 532 REJ09B0397-0300 Low 2 STC LDC ORC NOT OR ROTL ROTR NEG XOR AND SUB DEC SUBS CMP SUBX DAS XORC ANDC LDC ADD INC ADDS MOV ADDX ROTXR DAA 3 4 5 6 7 8 9 A B C D E F High 0 1 Table A.2 0 NOP SLEEP SHLL SHLR ROTXL 1 SHAL SHAR 2 MOV 3 BHI BLS BCC RTS BST BCLR BTST BOR MOV BIOR ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND BILD BXOR BAND BIST BLD EEPMOV Bit-manipulation instructions BSR RTE JMP MOV * BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT JSR BLE 4 BRA BRN Operation Code Map 5 MULXU DIVXU 6 BSET BNOT 7 8 9 A B C D E F Appendix A CPU Instruction Set Rev.3.00 Jul. 19, 2007 page 451 of 532 REJ09B0397-0300 Note: * The PUSH and POP instructions are identical in machine language to MOV instructions. Appendix A CPU Instruction Set A.3 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.4 indicates the number of states required for each cycle (instruction fetch, data read/write, etc.) in instruction execution, and table A.3 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2 + 1 x 2 = 8 L=M=N=0 Rev.3.00 Jul. 19, 2007 page 452 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Table A.3 Number of Cycles in Each Instruction Access Location On-Chip Memory SI SJ SK SL SM SN 1 2 or 3* 2 On-Chip Peripheral Module Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: * Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data Access for details. Rev.3.00 Jul. 19, 2007 page 453 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Table A.4 Number of Cycles in Each Instruction Byte Data Stack Instruction Branch Addr. Read Operation Access Fetch L K J I 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 1 Word Data Internal Operation Access N M Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd Rev.3.00 Jul. 19, 2007 page 454 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Byte Data Stack Instruction Branch Addr. Read Operation Access Fetch L K J I 2 2 1 2 1 1 2 2 Word Data Internal Operation Access N M Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd 1 2 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 1 1 BIXOR #xx:3, @aa:8 2 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 1 1 2 2 2 2 1 1 2 2 2 Rev.3.00 Jul. 19, 2007 page 455 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Byte Data Stack Instruction Branch Addr. Read Operation Access Fetch L K J I 2 2 1 2 2 1 2 2 1 2 2 1 2 1 1 1 1 1 1 2 2 1 2 Word Data Internal Operation Access N M Instruction Mnemonic BSET BSR BST BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 2 CMP CMP. B #xx:8, Rd CMP. B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 12 2n + 2* 1 2 2 2 Note: * n: Initial value in R4L. The source and destination operands are accessed n + 1 times each. Rev.3.00 Jul. 19, 2007 page 456 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Byte Data Stack Instruction Branch Addr. Read Operation Access Fetch L K J I 1 1 1 1 1 1 1 1 1 1 1 2 2 Word Data Internal Operation Access N M Instruction Mnemonic MOV MOV.B @Rs, Rd MOV.B @(d:16, Rs), 2 Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd 1 1 2 1 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 12 2 2 MOV.W @(d:16, Rs), 2 Rd MOV.W @Rs+, Rd 1 MOV.W @aa:16, Rd 2 MOV.W Rs, @Rd 1 MOV.W Rs, @(d:16, 2 Rd) MOV.W Rs, @-Rd 1 MOV.W Rs, @aa:16 2 MULXU NEG NOP NOT OR MULXU.B Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC ROTL ROTR ORC #xx:8, CCR ROTL.B Rd ROTR.B Rd 1 1 1 1 1 1 1 1 1 Rev.3.00 Jul. 19, 2007 page 457 of 532 REJ09B0397-0300 Appendix A CPU Instruction Set Byte Data Stack Instruction Branch Addr. Read Operation Access Fetch L K J I 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 2 2 Word Data Internal Operation Access N M Instruction Mnemonic ROTXL ROTXR RTE RTS SHAL SHAR SHLL SHLR SLEEP STC SUB ROTXL.B Rd ROTXR.B Rd RTE RTS SHAL.B Rd SHAR.B Rd SHLL.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd SUBS.W #2, Rd POP PUSH SUBX POP Rd PUSH Rs SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XORC XORC #xx:8, CCR Rev.3.00 Jul. 19, 2007 page 458 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.1 B.1.1 Register Addresses H8/3857 Group Addresses Bit Names Bit 6 SWE -- Bit 5 -- -- Bit 4 -- -- Bit 3 EV -- Bit 2 PV -- Bit 1 E ESU Bit 0 P PSU Module Name Flash memory Address Register (low) Name Bit 7 H'80 H'81 H'82 H'83 H'84 H'85 H'86 H'87 H'88 H'89 H'8A H'8B H'8C H'8D H'8E H'8F H'90 H'91 H'92 H'93 H'94 H'95 H'96 H'97 H'98 H'99 H'9A H'9B SYSCR3* 1 FLMCR1* FWE FLMCR2* FLER 1 1 EBR* 1 -- EB6 EB5 EB4 EB3 EB2 EB1 EB0 MDCR* 1 TSDS2 TSDS1 TCWE TCW6 B4WI TCW5 FLSHE WDON TCW2 CKS2 B0WI TCW1 CKS1 WRST TCW0 CKS0 Watchdog timer TCSRW* B6WI TCW* 2 2 TCSRWE B2WI TCW4 TCW3 TCW7 TMW* 2 Rev.3.00 Jul. 19, 2007 page 459 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers Address Register (low) Name Bit 7 H'9C H'9D H'9E H'9F H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 H'B8 TMA TCA TMB TMA7 TCA7 TMB7 TMA6 TCA6 TCB6/ TLB6 TMC6 TCC6/ TLC6 CKSH2 CMFH TCFH6 TMA5 TCA5 TCB5/ TLB5 TMC5 TCC5/ TLC5 CKSH1 OVIEH TCFH5 TCA4 TCB4/ TLB4 TCC4/ TLC4 CKSH0 CCLRH TCFH4 TMA3 TCA3 TCB3/ TLB3 TCC3/ TLC3 TOLL OVFL TCFH3 TMA2 TCA2 TMB2 TCB2/ TLB2 TMC2 TCC2/ TLC2 CKSL2 CMFL TCFH2 TMA1 TCA1 TMB1 TCB1/ TLB1 TMC1 TCC1/ TLC1 CKSL1 OVIEL TCFH1 TMA0 TCA0 TMB0 TCB0/ TLB0 TMC0 TCC0/ TLC0 CKSL0 CCLRL TCFH0 Timer F Timer C Timer B Timer A SMR BRR SCR3 TDR SSR RDR COM BRR7 TIE TDR7 TDRE RDR7 CHR BRR6 RIE TDR6 RDRF RDR6 PE BRR5 TE TDR5 OER RDR5 PM BRR4 RE TDR4 FER RDR4 STOP BRR3 MPIE TDR3 PER RDR3 MP BRR2 TEIE TDR2 TEND RDR2 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 SCI3 SCR1 SCSR1 SDRU SDRL SNC1 SDRU7 SDRL7 SNC0 SOL SDRU6 SDRL6 ORER SDRU5 SDRL5 SDRU4 SDRL4 CKS3 SDRU3 SDRL3 CKS2 SDRU2 SDRL2 CKS1 SDRU1 SDRL1 CKS0 STF SDRU0 SDRL0 SCI1 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TCB/TLB TCB7/ TLB7 TMC TMC7 TCC/TLC TCC7/ TLC7 TCRF TCSRF TCFH TOLH OVFH TCFH7 Rev.3.00 Jul. 19, 2007 page 460 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers Address Register (low) Name Bit 7 H'B9 H'BA H'BB H'BC H'BD H'BE H'BF H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 H'D8 H'D9 PDR1 PDR2 PDR3 PDR4 PDR5 P17 P27 P37 P57 P16 P26 P36 P56 P15 P25 P35 P55 P14 P24 P34 P54 P13 P23 P33 P43 P53 P12 P22 P32 P42 P52 P11 P21 P31 P41 P51 P10 P20 P30 P40 P50 I/O ports PWCR PWCR0 PWDRU PWDRL 14-bit PWM PMR1 PMR2 PMR3 PMR4 PMR5 IRQ3 IRQ2 IRQ1 PWM IRQ0 TMOFH TMOFL POF1 SO1 UD SI1 TMOW IRQ4 SCK1 I/O ports AMR ADRR ADSR CKS ADR7 ADSF TRGE ADR6 ADR5 ADR4 CH3 ADR3 CH2 ADR2 CH1 ADR1 CH0 ADR0 A/D converter TCFL OCRFH OCRFL TCFL7 Bit Names Bit 6 TCFL6 Bit 5 TCFL5 Bit 4 TCFL4 Bit 3 TCFL3 Bit 2 TCFL2 Bit 1 TCFL1 Bit 0 TCFL0 Module Name Timer F OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Rev.3.00 Jul. 19, 2007 page 461 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers Address Register (low) Name Bit 7 H'DA H'DB H'DC H'DD H'DE H'DF H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 IRR1 IRR2 IRRTA IRRDT IRRS1 IRRAD IRRI4 IRRI3 IRRI2 IRRI1 IRRTC IRRI0 IRRTB SYSCR1 SSBY SYSCR2 IEGR IENR1 IENR2 IENTA IENDT STS2 IENS1 IENAD STS1 IENWP STS0 NESEL IEG4 IEN4 LSON DTON IEG3 IEN3 MSON IEG2 IEN2 SA1 IEG1 IEN1 IENTC SA0 IEG0 IEN0 IENTB System control PCR9 PCRA PCR97 PCR96 PCR95 PCR94 PCR93 PCRA3 PCR92 PCRA2 PCR91 PCRA1 PCR90 PCRA0 PCR1 PCR2 PCR3 PCR4 PCR5 PCR17 PCR27 PCR37 PCR57 PCR16 PCR26 PCR36 PCR56 PCR15 PCR25 PCR35 PCR55 PCR14 PCR24 PCR34 PCR54 PCR13 PCR23 PCR33 PCR53 PCR12 PCR22 PCR32 PCR42 PCR52 PCR11 PCR21 PCR31 PCR41 PCR51 PCR10 PCR20 PCR30 PCR40 PCR50 PUCR1 PUCR3 PUCR5 PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PDR9 PDRA PDRB P97 PB7 P96 PB6 P95 PB5 P94 PB4 P93 PA3 PB3 P92 PA2 PB2 P91 PA1 PB1 P90 PA0 PB0 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name I/O ports IENTFH IENTFL IRRTFH IRRTFL Rev.3.00 Jul. 19, 2007 page 462 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers Address Register (low) Name Bit 7 H'FA H'FB H'FC H'FD H'FE H'FF Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Legend: SCI1: Serial communication interface 1 SCI3: Serial communication interface 3 Notes: 1. Applies to the F-ZTAT version. In the mask ROM version, a read access to the address of a register other than MDCR will always return 0, a read access to the MDCR address will return an undefined value, and writes are invalid. 2. Applies to the F-ZTAT version. In the mask ROM version, read accesses to the corresponding addresses will always return 1, and writes are invalid. Rev.3.00 Jul. 19, 2007 page 463 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers B.1.2 H8/3854 Group Addresses Bit Names Bit 6 SWE Bit 5 Bit 4 Bit 3 EV Bit 2 PV Bit 1 E ESU Bit 0 P PSU Module Name Flash memory Address Register (low) Name Bit 7 H'80 H'81 H'82 H'83 H'84 H'85 H'86 H'87 H'88 H'89 H'8A H'8B H'8C H'8D H'8E H'8F H'90 H'91 H'92 H'93 H'94 H'95 H'96 H'97 H'98 H'99 H'9A H'9B H'9C H'9D H'9E H'9F SYSCR3* 1 FLMCR1* FWE FLMCR2* FLER 1 1 EBR* 1 EB6 EB5 EB4 EB3 EB2 EB1 EB0 MDCR* 1 TSDS2 TSDS1 TCWE TCW6 B4WI TCW5 FLSHE WDON TCW2 CKS2 B0WI TCW1 CKS1 WRST TCW0 CKS0 Watchdog timer TCSRW* B6WI TCW* 2 2 TCSRWE B2WI TCW4 TCW3 TCW7 TMW* 2 Rev.3.00 Jul. 19, 2007 page 464 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers Address Register (low) Name Bit 7 H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 H'B8 H'B9 H'BA H'BB H'BC H'BD H'BE H'BF H'C0 H'C1 TCRF TCSRF TCFH TCFL OCRFH OCRFL TOLH OVFH TCFH7 TCFL7 CKSH2 CMFH TCFH6 TCFL6 CKSH1 OVIEH TCFH5 TCFL5 CKSH0 CCLRH TCFH4 TCFL4 TOLL OVFL TCFH3 TCFL3 CKSL2 CMFL TCFH2 TCFL2 CKSL1 OVIEL TCFH1 TCFL1 CKSL0 CCLRL TCFH0 TCFL0 Timer F TMA TCA TMB TMA7 TCA7 TMB7 TMA6 TCA6 TCB6/ TLB6 TMA5 TCA5 TCB5/ TLB5 TCA4 TCB4/ TLB4 TMA3 TCA3 TCB3/ TLB3 TMA2 TCA2 TMB2 TCB2/ TLB2 TMA1 TCA1 TMB1 TCB1/ TLB1 TMA0 TCA0 TMB0 TCB0/ TLB0 Timer B Timer A SMR BRR SCR3 TDR SSR RDR COM BRR7 TIE TDR7 TDRE RDR7 CHR BRR6 RIE TDR6 RDRF RDR6 PE BRR5 TE TDR5 OER RDR5 PM BRR4 RE TDR4 FER RDR4 STOP BRR3 MPIE TDR3 PER RDR3 MP BRR2 TEIE TDR2 TEND RDR2 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 SCI3 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TCB/TLB TCB7/ TLB7 OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Rev.3.00 Jul. 19, 2007 page 465 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers Address Register (low) Name Bit 7 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 H'D8 H'D9 H'DA H'DB H'DC H'DD H'DE H'DF H'E0 H'E1 H'E2 H'E3 PUCR5 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PUCR1 PUCR17 PUCR15 PUCR12 PUCR11 PUCR10 PDR9 PDRA PDRB P97 PB7 P96 PB6 P95 PB5 P94 PB4 P93 PA3 P92 PA2 P91 PA1 P90 PA0 PDR4 PDR5 P57 P56 P55 P54 P43 P53 P42 P52 P41 P51 P40 P50 PDR1 PDR2 P17 P27 P26 P15 P25 P24 P23 P12 P22 P11 P21 P10 P20 I/O ports PMR4 PMR5 NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 PMR1 PMR2 IRQ3 IRQ1 IRQ0 TMOFH TMOFL TMOW IRQ4 I/O ports AMR ADRR ADSR CKS ADR7 ADSF TRGE ADR6 ADR5 ADR4 CH3 ADR3 CH2 ADR2 CH1 ADR1 CH0 ADR0 A/D converter Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Rev.3.00 Jul. 19, 2007 page 466 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers Address Register (low) Name Bit 7 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 IRR1 IRR2 IRRTA IRRDT IRRAD IRRI4 IRRI3 IRRI1 IRRI0 IRRTB SYSCR1 SSBY SYSCR2 IEGR IENR1 IENR2 IENTA IENDT STS2 IENAD STS1 IENWP STS0 NESEL IEG4 IEN4 LSON DTON IEG3 IEN3 MSON SA1 IEG1 IEN1 SA0 IEG0 IEN0 IENTB System control PCR9 PCRA PCR97 PCR96 PCR95 PCR94 PCR93 PCRA3 PCR92 PCRA2 PCR91 PCRA1 PCR90 PCRA0 PCR4 PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR42 PCR52 PCR41 PCR51 PCR40 PCR50 PCR1 PCR2 PCR17 PCR27 Bit Names Bit 6 PCR26 Bit 5 PCR15 PCR25 Bit 4 PCR24 Bit 3 PCR23 Bit 2 PCR12 PCR22 Bit 1 PCR11 PCR21 Bit 0 PCR10 PCR20 Module Name I/O ports IENTFH IENTFL IRRTFH IRRTFL Legend: SCI3: Serial communication interface 3 Notes: 1. Applies to the F-ZTAT version. In the mask ROM version, a read access to the address of a register other than MDCR will always return 0, a read access to the MDCR address will return an undefined value, and writes are invalid. 2. Applies to the F-ZTAT version. In the mask ROM version, read accesses to the corresponding addresses will always return 1, and writes are invalid. Rev.3.00 Jul. 19, 2007 page 467 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers B.2 Register Descriptions Register name Address to which the register is mapped Name of on-chip supporting module Timer C Register acronym TMC--Timer mode register C H'B4 Bit numbers Bit 7 TMC7 Initial value Read/Write 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 1 3 1 2 TMC2 0 R/W 1 TMC1 0 R/W 0 TMC0 0 R/W Initial bit values Names of the bits. Dashes () indicate reserved bits. Possible types of access R W Read only Write only R/W Read and write Clock select 0 0 0 Internal clock: /8192 1 Internal clock: /2048 1 0 Internal clock: /512 1 Internal clock: /64 1 0 0 Internal clock: /16 1 Internal clock: /4 1 0 Internal clock: W/4 1 External event (TMIC): Rising or falling edge Counter up/down control 0 0 TCC is an up-counter 1 TCC is a down-counter 1 * TCC up/down control is determined by input at pin UD. TCC is a down-counter if the UD input is high, and an up-counter if the UD input is low. Legend: * Don't care Auto-reload function select 0 Interval function selected 1 Auto-reload function selected Full name of bit Descriptions of bit settings Rev.3.00 Jul. 19, 2007 page 468 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers FLMCR1--Flash memory control register 1 H'80 Flash memory (On-chip flash memory version only) 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Bit : 7 FWE * R 6 SWE 0 R/W 5 0 4 0 Initial value : Read/Write : Program 0 1 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase 0 1 Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Program-verify 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Erase -verify 0 1 Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Software write enable 0 1 Programmin/disabled Programming enabled [Setting condition] When FWE = 1 Flash write enable 0 1 When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Note: * Determined by the state of the FWE pin. Rev.3.00 Jul. 19, 2007 page 469 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers FLMCR2--Flash memory control register 2 H'81 Flash memory (On-chip flash memory version only) 3 0 2 0 1 ESU 0 R/W 0 PSU 0 R/W Bit : 7 FLER 0 R 6 0 5 0 4 0 Initial value : Read/Write : Program setup 0 1 Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE = 1 Erase setup 0 1 Erase setup cleared Erase setup [Setting condition] When FWE = 1 and SWE = 1 Flash memory error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode An error occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 6.6.3, Error Protection 1 Rev.3.00 Jul. 19, 2007 page 470 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers EBR--Erase block register H'83 Flash memory (On-chip flash memory version only) 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W Bit : 7 0 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W Initial value : Read/Write : Flash memory erase blocks Block (Size) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (12 kbytes) Addresses H'0000 to H'03FF H'0400 to H'07FF H'0800 to H'0BFF H'0C00 to H'0FFF H'1000 to H'7FFF H'8000 to H'BFFF H'C000 to H'EDFF Rev.3.00 Jul. 19, 2007 page 471 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers MDCR--Mode control register H'89 Flash memory (On-chip flash memory version only) 3 0 2 0 1 TSDS2 * R 0 TSDS1 * R Bit : 7 0 6 0 5 0 4 0 Initial value : Read/Write : Note: * Determined by the TEST and TEST2 pins. Test pin monitor bits SYSCR3--System control register 3 H'8F Flash memory (On-chip flash memory version only) 3 2 0 1 0 0 0 Bit : 7 0 6 0 5 0 4 0 FLSHE 0 R/W Initial value : Read/Write : Flash memory control register enable 0 1 Flash memory control registers are unselected Flash memory control registers are selected Rev.3.00 Jul. 19, 2007 page 472 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers TCSRW--Timer control/status register W H'90 Flash memory (On-chip flash memory version only) 3 2 WDON 0 R/(W)* 1 B0WI 1 R 0 WRST 0 R/(W)* Bit : 7 B6WI 6 TCWE 0 R/(W)* 5 4 B4WI TCSRWE B2WI 1 R 0 R/(W)* 1 R Initial value : Read/Write : 1 R Watchdog timer reset [Clearing conditions] 0 * Reset by RES pin * When 0 is written to WRST while writing 0 to B0WI when TCSRWE = 1 [Setting condition] 1 When TCW overflows and an internal reset signal is generated Bit 0 write inhibit 0 Writing to bit 0 is enabled 1 Writing to bit 0 is disabled Watchdog timer on 0 Watchdog timer operation is disabled 1 Watchdog timer operation is enabled Bit 2 write inhibit 0 Writing to bit 2 is enabled 1 Writing to bit 2 is disabled Timer control/status register W write enable 0 Writing to bits 2 and 0 is disabled 1 Writing to bits 2 and 0 is enabled Bit 4 write inhibit 0 Writing to bit 4 is enabled 1 Writing to bit 4 is disabled Timer counter W write enable 0 Writing of data to TCW is disabled 1 Writing of data to TCW is enabled Bit 6 write inhibit 0 Writing to bit 6 is enabled 1 Writing to bit 6 is disabled Note: * Can be written to only when the write condition is satisfied. Rev.3.00 Jul. 19, 2007 page 473 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers TCW--Timer counter W H'91 Flash memory (On-chip flash memory version only) 3 2 TCW2 0 R/W 1 TCW1 0 R/W 0 TCW0 0 R/W Bit : 7 TCW7 6 TCW6 0 R/W 5 TCW5 0 R/W 4 TCW4 0 R/W TCW3 0 R/W Initial value : Read/Write : 0 R/W Count value TMW--Timer mode register W H'92 Flash memory (On-chip flash memory version only) 3 1 2 CKS2 1 R/W 1 CKS1 1 R/W 0 CKS0 1 R/W Bit : 7 6 1 5 1 4 1 Initial value : Read/Write : 1 Clock select Bit 1 Bit 2 CKS1 CKS2 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Description Internal clock: /64 Internal clock: /128 Internal clock: /256 Internal clock: /512 Internal clock: /1024 Internal clock: /2048 Internal clock: /4096 Internal clock: /8192 (initial value) Note: TMW is an 8-bit read/write register that selects the input clock. Upon reset, TMW is initialized to H'FF. Rev.3.00 Jul. 19, 2007 page 474 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers SCR1--Serial control register 1 H'A0 SCI1 (H8/3857 Group only) 2 1 CKS1 0 R/W 0 CKS0 0 R/W Bit Initial value Read/Write 7 SNC1 0 R/W 6 SNC0 0 R/W 5 0 R/W 4 0 R/W 3 CKS3 0 R/W CKS2 0 R/W Clock Select (CKS2 to CKS0) Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Serial Clock Cycle Synchronous Prescaler Division = 5 MHz = 2.5 MHz /1024 204.8 s 409.6 s /256 51.2 s 102.4 s 12.8 s 25.6 s /64 6.4 s 12.8 s /32 3.2 s 6.4 s /16 1.6 s 3.2 s /8 0.8 s 1.6 s /4 0.8 s /2 Clock source select 0 Clock source is prescaler S, and pin SCK 1 is output pin 1 Clock source is external clock, and pin SCK 1 is input pin Operation mode select 0 0 8-bit synchronous transfer mode 1 16-bit synchronous transfer mode 1 0 Continuous clock output mode 1 Reserved Rev.3.00 Jul. 19, 2007 page 475 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers SCSR1--Serial control/status register 1 H'A1 SCI1 (H8/3857 Group only) 1 0 0 STF 0 R/W Bit Initial value Read/Write 7 1 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 0 Start flag 0 Read Write 1 Read Write 3 0 2 0 Indicates that transfer is stopped Invalid Indicates transfer in progress Starts a transfer operation Overrun error flag 0 [Clearing condition] After reading 1, cleared by writing 0 1 [Setting condition] Set if a clock pulse is input after transfer is complete, when an external clock is used Extended data bit 0 Read SO 1 pin output level is low Write SO 1 pin output level changes to low 1 Read SO 1 pin output level is high Write SO 1 pin output level changes to high Note: * Only a write of 0 for flag clearing is possible. Rev.3.00 Jul. 19, 2007 page 476 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers SDRU--Serial data register U H'A2 SCI1 (H8/3857 Group only) 2 1 SDRU1 R/W 0 SDRU0 R/W Bit Initial value Read/Write 7 SDRU7 R/W 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3 SDRU3 R/W SDRU2 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Used to set transmit data and store receive data 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data SDRL--Serial data register L H'A3 SCI1 (H8/3857 Group only) 2 1 SDRL1 R/W 0 SDRL0 R/W Bit Initial value Read/Write 7 SDRL7 R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 SDRL3 R/W SDRL2 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Used to set transmit data and store receive data 8-bit transfer mode: 8-bit data 16-bit transfer mode: Lower 8 bits of data Rev.3.00 Jul. 19, 2007 page 477 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers SMR--Serial mode register Bit Initial value Read/Write 7 COM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 STOP 0 R/W H'A8 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI3 CKS0 0 R/W Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit adding and checking disabled 1 Parity bit adding and checking enabled Character length 0 8-bit data 1 7-bit data Communication mode 0 Asynchronous mode 1 Synchronous mode Clock select 0, 1 0 0 clock 1 /4 clock 1 0 /16 clock 1 /64 clock BRR--Bit rate register Bit Initial value Read/Write 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W H'A9 2 BRR2 1 R/W 1 BRR1 1 R/W 0 SCI3 BRR0 1 R/W Rev.3.00 Jul. 19, 2007 page 478 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers SCR3--Serial control register 3 Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W H'AA 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI3 CKE0 0 R/W Clock enable Bit 1 CKE1 0 Bit 0 CKE0 0 1 Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Transmit end interrupt enable 0 1 0 Transmit end interrupt (TEI) disabled Transmit end interrupt (TEI) enabled Multiprocessor interrupt request disabled (ordinary receive operation) [Clearing condition] Multiprocessor bit receives a data value of 1 Multiprocessor interrupt request enabled Until a multiprocessor bit value of 1 is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are disabled, and serial status register (SSR) flags RDRF, FER, and OER are not set. Receive operation disabled (RXD is a general I/O port) Receive operation enabled (RXD is the receive data pin) Transmit operation disabled (TXD is a general I/O port) Transmit operation enabled (TXD is the transmit data pin) Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled Transmit data empty interrupt request (TXI) disabled Transmit data empty interrupt request (TXI) enabled Description Clock Source Internal clock Internal clock Internal clock Reserved (Do not set this combination) External clock External clock Reserved (Do not set this combination) Reserved (Do not set this combination) SCK 3 Pin Function I/O port Serial clock output Clock output Reserved (Do not set this combination) Clock input Serial clock input Reserved (Do not set this combination) Reserved (Do not set this combination) 1 0 1 Multiprocessor interrupt enable 1 Receive enable 0 1 0 1 0 1 0 1 Transmit enable Receive interrupt enable Transmit interrupt enable Rev.3.00 Jul. 19, 2007 page 479 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers TDR--Transmit data register Bit Initial value Read/Write 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W H'AB 2 TDR2 1 R/W 1 TDR1 1 R/W 0 SCI3 TDR0 1 R/W Data to be transferred to TSR Rev.3.00 Jul. 19, 2007 page 480 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers SSR--Serial status register Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 OER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* H'AC 2 TEND 1 R 1 MPBR 0 R 0 MPBT 0 R/W SCI3 Multiprocessor bit receive 0 Indicates reception of data in which the multiprocessor bit is 0 1 Indicates reception of data in which the multiprocessor bit is 1 Multiprocessor bit transmit 0 The multiprocessor bit in transmit data is 0 1 The multiprocessor bit in transmit data is 1 Transmit end 0 Indicates that transmission is in progress [Clearing conditions] After reading TDRE = 1, cleared by writing 0 to TDRE. When data is written to TDR by an instruction. 1 Indicates that a transmission has ended [Setting conditions] When bit TE in serial control register 3 (SCR3) is 0. If TDRE is set to 1 when the last bit of a transmitted character is sent. Parity error 0 Indicates that data receiving is in progress or has been completed [Clearing condition] After reading PER = 1, cleared by writing 0 1 Indicates that a parity error occurred in data receiving [Setting condition] When the sum of 1s in received data plus the parity bit does not match the parity mode bit (PM) setting in the serial mode register (SMR) Framing error 0 Indicates that data receiving is in progress or has been completed [Clearing condition] After reading FER = 1, cleared by writing 0 1 Indicates that a framing error occurred in data receiving [Setting condition] The stop bit at the end of receive data is checked and found to be 0 Overrun error 0 Indicates that data receiving is in progress or has been completed [Clearing condition] After reading OER = 1, cleared by writing 0 1 Indicates that an overrun error occurred in data receiving [Setting condition] When reception of the next serial data is completed while RDRF is set to 1 Receive data register full 0 Indicates there is no receive data in RDR [Clearing conditions] After reading RDRF = 1, cleared by writing 0. When data is read from RDR by an instruction. 1 Indicates that there is receive data in RDR [Setting condition] When receiving ends normally, with receive data transferred from RSR to RDR Transmit data register empty 0 Indicates that transmit data written to TDR has not been transferred to TSR [Clearing conditions] After reading TDRE = 1, cleared by writing 0. When data is written to TDR by an instruction. 1 Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR [Setting conditions] When bit TE in serial control register 3 (SCR3) is 0. When data is transferred from TDR to TSR. Note: * Only a write of 0 for flag clearing is possible. Rev.3.00 Jul. 19, 2007 page 481 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers RDR--Receive data register Bit Initial value Read/Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R H'AD 2 RDR2 0 R 1 RDR1 0 R 0 SCI3 RDR0 0 R TMA--Timer mode register A Bit Initial value Read/Write 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- 3 H'B0 2 TMA2 0 R/W 1 TMA1 0 R/W Timer A 0 TMA0 0 R/W TMA3 0 R/W Clock output select 0 0 0 /32 1 /16 1 0 /8 1 /4 1 0 0 W /32 1 W /16 1 0 W /8 1 W /4 Internal clock select Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period 0 0 0 /8192 0 PSS 1 /4096 PSS /2048 PSS 1 0 /512 PSS 1 1 0 0 /256 PSS 1 /128 PSS /32 1 0 PSS /8 1 PSS 0 0 0 1s 1 PSW 1 0.5 s PSW 0.25 s 1 0 PSW 0.03125 s 1 PSW 1 0 0 PSW and TCA are reset 1 1 0 1 Function Interval timer Time base Rev.3.00 Jul. 19, 2007 page 482 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers TCA--Timer counter A Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R H'B1 2 TCA2 0 R 1 TCA1 0 R Timer A 0 TCA0 0 R Count value TMB--Timer mode register B Bit Initial value Read/Write 7 TMB7 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'B2 2 TMB2 0 R/W 1 TMB1 0 R/W Timer B 0 TMB0 0 R/W Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected Clock select 0 0 0 Internal clock: /8192 1 Internal clock: /2048 1 0 Internal clock: /512 1 Internal clock: /256 1 0 0 Internal clock: /64 1 Internal clock: /16 1 0 Internal clock: /4 1 External event (TMIB): Rising or falling edge Rev.3.00 Jul. 19, 2007 page 483 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers TCB--Timer counter B Bit Initial value Read/Write 7 TCB7 0 R 6 TCB6 0 R 5 TCB5 0 R 4 TCB4 0 R 3 TCB3 0 R H'B3 2 TCB2 0 R 1 TCB1 0 R Timer B 0 TCB0 0 R Count value TLB--Timer load register B Bit Initial value Read/Write 7 TLB7 0 W 6 TLB6 0 W 5 TLB5 0 W 4 TLB4 0 W 3 TLB3 0 W H'B3 2 TLB2 0 W 1 TLB1 0 W Timer B 0 TLB0 0 W Reload value Rev.3.00 Jul. 19, 2007 page 484 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers TMC--Timer mode register C H'B4 Timer C (H8/3857 Group only) 2 1 TMC1 0 R/W 0 TMC0 0 R/W Bit Initial value Read/Write 7 TMC7 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 1 3 1 TMC2 0 R/W Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected Clock select 0 0 0 Internal clock: /8192 1 Internal clock: /2048 1 0 Internal clock: /512 1 Internal clock: /64 1 0 0 Internal clock: /16 1 Internal clock: /4 1 0 Internal clock: W/4 1 External event (TMIC): Rising or falling edge Counter up/down control 0 0 TCC is an up-counter 1 TCC is a down-counter 1 * TCC up/down operation is hardware-controlled by input at the UD pin. TCC is a down-counter if the UD input is high, and an up-counter if the UD input is low. Legend: * Don't care TCC--Timer counter C H'B5 Timer C (H8/3857 Group only) 2 1 TCC1 0 R 0 TCC0 0 R Bit Initial value Read/Write 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R TCC2 0 R Count value Rev.3.00 Jul. 19, 2007 page 485 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers TLC--Timer load register C H'B5 Timer C (H8/3857 Group only) 2 1 TLC1 0 W 0 TLC0 0 W Bit Initial value Read/Write 7 TLC7 0 W 6 TLC6 0 W 5 TLC5 0 W 4 TLC4 0 W 3 TLC3 0 W TLC2 0 W Reload value TCRF--Timer control register F Bit Initial value Read/Write 7 TOLH 0 W 6 CKSH2 0 W 5 CKSH1 0 W 4 CKSH0 0 W 3 TOLL 0 W H'B6 2 CKSL2 0 W 1 CKSL1 0 W Timer F 0 CKSL0 0 W Toggle output level H 0 Low level 1 High level Clock select L 0 * * External event (TMIF): Rising or falling edge 1 0 0 Internal clock: /32 1 Internal clock: /16 1 0 Internal clock: /4 1 Internal clock: /2 Toggle output level L 0 Low level 1 High level Clock select H 0 * * 16-bit mode selected. TCFL overflow signals are counted. 1 0 0 Internal clock: /32 1 Internal clock: /16 1 0 Internal clock: /4 1 Internal clock: /2 Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 486 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers TCSRF--Timer control/status register F Bit Initial value Read/Write 7 OVFH 0 R/(W)* 6 CMFH 0 R/(W)* 5 OVIEH 0 R/W 4 CCLRH 0 R/W 3 OVFL 0 R/(W)* H'B7 2 CMFL 0 R/(W)* 1 OVIEL 0 R/W Timer F 0 CCLRL 0 R/W Timer overflow interrupt enable L 0 TCFL overflow interrupt disabled 1 TCFL overflow interrupt enabled Compare match flag L 0 [Clearing condition] After reading CMFL = 1, cleared by writing 0 to CMFL 1 [Setting condition] When the TCFL value matches the OCRFL value Timer overflow flag L 0 [Clearing condition] After reading OVFL = 1, cleared by writing 0 to OVFL 1 [Setting condition] When the value of TCFL goes from H'FF to H'00 Counter clear H 0 16-bit mode: 8-bit mode: 1 16-bit mode: 8-bit mode: TCF clearing by compare match disabled TCFH clearing by compare match disabled TCF clearing by compare match enabled TCFH clearing by compare match enabled Counter clear L 0 TCFL clearing by compare match disabled 1 TCFL clearing by compare match enabled Timer overflow interrupt enable H 0 TCFH overflow interrupt disabled 1 TCFH overflow interrupt enabled Compare match flag H 0 [Clearing condition] After reading CMFH = 1, cleared by writing 0 to CMFH 1 [Setting condition] When the TCFH value matches the OCRFH value Timer overflow flag H 0 [Clearing condition] After reading OVFH = 1, cleared by writing 0 to OVFH 1 [Setting condition] When the value of TCFH goes from H'FF to H'00 Note: * Only a write of 0 for flag clearing is possible. Rev.3.00 Jul. 19, 2007 page 487 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers TCFH--8-bit timer counter FH Bit Initial value Read/Write 7 TCFH7 0 R/W 6 TCFH6 0 R/W 5 TCFH5 0 R/W 4 TCFH4 0 R/W 3 H'B8 2 TCFH2 0 R/W 1 TCFH1 0 R/W Timer F 0 TCFH0 0 R/W TCFH3 0 R/W Count value TCFL--8-bit timer counter FL Bit Initial value Read/Write 7 TCFL7 0 R/W 6 TCFL6 0 R/W 5 TCFL5 0 R/W 4 TCFL4 0 R/W 3 H'B9 2 TCFL2 0 R/W 1 TCFL1 0 R/W Timer F 0 TCFL0 0 R/W TCFL3 0 R/W Count value OCRFH--Output compare register FH Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'BA 2 1 R/W 1 1 R/W Timer F 0 1 R/W OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 OCRFL--Output compare register FL Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'BB 2 1 R/W 1 1 R/W Timer F 0 1 R/W OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Rev.3.00 Jul. 19, 2007 page 488 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers AMR--A/D mode register Bit Initial value Read/Write 7 CKS 0 R/W 6 TRGE 0 R/W 5 1 4 1 3 CH3 0 R/W H'C4 2 CH2 0 R/W 1 A/D converter 0 CH0 0 R/W CH1 0 R/W Channel select Bit 3 Bit 2 Bit 1 CH3 CH2 CH1 0 0 * 1 0 1 1 0 0 1 1 External trigger select 1 * Bit 0 CH0 * 0 1 0 1 0 1 0 1 * Analog input channel No channel selected AN 0 *1 AN 1 *1 AN 2 *1 AN 3 *1 AN 4 AN 5 AN 6 AN 7 Reserved 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select Bit 7 CKS Conversion Period 0 62/ 1 31/ Conversion Time = 2 MHz = 5 MHz 31 s 15.5 s 12.4 s *2 Legend: * Don't care Notes: 1. AN0 to AN3 can be selected in the H8/3857 Group only. They must not be selected in the H8/3854 Group. 2. Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a value of at least 12.4 s. Rev.3.00 Jul. 19, 2007 page 489 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers ADRR--A/D result register Bit Initial value Read/Write 7 ADR7 R 6 ADR6 R 5 ADR5 R 4 ADR4 R 3 ADR3 R H'C5 2 ADR2 R 1 A/D converter 0 ADR0 R ADR1 R Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A/D conversion result ADSR--A/D start register Bit Initial value Read/Write 7 ADSF 0 R/W 6 1 5 1 4 1 3 1 H'C6 2 1 1 1 A/D converter 0 1 A/D status flag 0 Read Indicates the completion of A/D conversion Write Stops A/D conversion 1 Read Indicates A/D conversion in progress Write Starts A/D conversion Rev.3.00 Jul. 19, 2007 page 490 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers PMR1--Port mode register 1 Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2* 0 R/W 5 IRQ1 0 R/W 4 PWM* 0 R/W 3 0 H'C8 2 TMOFH 0 R/W 1 TMOFL 0 R/W I/O ports 0 TMOW 0 R/W P10 /TMOW pin function switch 0 Functions as P10 I/O pin 1 Functions as TMOW output pin P11 /TMOFL pin function switch 0 Functions as P11 I/O pin 1 Functions as TMOFL output pin P12 /TMOFH pin function switch 0 Functions as P12 I/O pin 1 Functions as TMOFH input pin P14 /PWM pin function switch 0 Functions as P14 I/O pin 1 Functions as PWM output pin P15 /IRQ 1 /TMIB pin function switch 0 Functions as P15 I/O pin 1 Functions as IRQ 1 /TMIB input pin P16 /IRQ 2 /TMIC pin function switch 0 Functions as P16 I/O pin 1 Functions as IRQ 2 /TMIC input pin P17 /IRQ 3 /TMIF pin function switch 0 Functions as P17 I/O pin 1 Functions as IRQ 3 /TMIF input pin Note: * IRQ2 and PWM are functions of the H8/3857 Group only. In the H8/3854 Group these bits are reserved, and must always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 491 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers PMR2--Port mode register 2 Bit Initial value Read/Write 7 1 6 1 5 0 R/W 4 0 R/W 3 IRQ0 0 R/W H'C9 2 POF1* 0 R/W 1 UD* 0 R/W I/O ports 0 IRQ4 0 R/W P20 /IRQ 4 /ADTRG pin function switch 0 Functions as P20 I/O pin 1 Functions as IRQ 4 /ADTRG input pin P21 /UD pin function switch 0 Functions as P21 I/O pin 1 Functions as UD input pin P32 /SO 1 pin PMOS control 0 CMOS output 1 NMOS open-drain output P43 /IRQ 0 pin function switch 0 Functions as P4 3 input pin 1 Functions as IRQ 0 input pin Note: * POF1 and UD are functions of the H8/3857 Group only. In the H8/3854 Group these bits are reserved, and must always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 492 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers PMR3--Port mode register 3 H'CA I/O ports (H8/3857 Group only) 1 SI1 0 R/W 0 SCK1 0 R/W Bit Initial value Read/Write 7 0 6 0 5 0 4 0 3 0 2 SO1 0 R/W P3 0 /SCK 1 pin function switch 0 Functions as P3 0 I/O pin 1 Functions as SCK 1 I/O pin P3 1 /SI 1 pin function switch 0 Functions as P3 1 I/O pin 1 Functions as SI 1 input pin P3 2 /SO 1 pin function switch 0 Functions as P3 2 I/O pin 1 Functions as SO 1 output pin PMR4--Port mode register 4 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'CB 2 0 R/W 1 0 R/W I/O ports 0 0 R/W NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 0 P2 n has CMOS output 1 P2 n has NMOS open-drain output Rev.3.00 Jul. 19, 2007 page 493 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers PMR5--Port mode register 5 Bit Initial value Read/Write 7 WKP7 0 R/W 6 WKP6 0 R/W 5 WKP5 0 R/W 4 WKP4 0 R/W 3 WKP3 0 R/W H'CC 2 WKP2 0 R/W 1 WKP1 0 R/W I/O ports 0 WKP0 0 R/W P5n /WKPn pin function switch 0 Functions as P5 n I/O pin 1 Functions as WKPn input pin PWCR--PWM control register H'D0 14-bit PWM (H8/3857 Group only) 2 1 1 0 PWCR0 0 W Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 1 Clock select 0 The input clock is /2 (t* = 2/). The conversion period is 16,384/, with a minimum modulation width of 1/ 1 The input clock is /4 (t* = 4/). The conversion period is 32,768/, with a minimum modulation width of 2/ Note: * t: Period of PWM input clock PWDRU--PWM data register U H'D1 14-bit PWM (H8/3857 Group only) 2 0 1 0 W 0 0 W Bit Initial value Read/Write 7 1 6 1 5 0 W 4 0 W 3 0 W PWDRU5 PWDRU4PWDRU3 PWDRU2 PWDUR1 PWDRU0 W Upper 6 bits of data for generating PWM waveform Rev.3.00 Jul. 19, 2007 page 494 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers PWDRL--PWM data register L H'D2 14-bit PWM (H8/3857 Group only) 2 0 1 0 W 0 0 W Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 W Lower 8 bits of data for generating PWM waveform PDR1--Port data register 1 Bit Initial value Read/Write 7 P17 0 R/W 6 P16* 0 R/W 5 P15 0 R/W 4 P14* 0 R/W 3 P13* 0 R/W H'D4 2 P12 0 R/W 1 P11 0 R/W I/O ports 0 P10 0 R/W Note: * P16, P14, and P13 are functions of the H8/3857 Group only. In the H8/3854 Group these bits are reserved, and must always be set to 1. PDR2--Port data register 2 Bit Initial value Read/Write 7 P27 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 P23 0 R/W H'D5 2 P22 0 R/W 1 P21 0 R/W I/O ports 0 P20 0 R/W PDR3--Port data register 3 H'D6 I/O ports (H8/3857 Group only) 2 1 P31 0 R/W 0 P30 0 R/W Bit Initial value Read/Write 7 P37 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W P32 0 R/W Rev.3.00 Jul. 19, 2007 page 495 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers PDR4--Port data register 4 Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 P43 H'D7 2 P42 0 R/W 1 P41 0 R/W I/O ports 0 P40 0 R/W Undefined R PDR5--Port data register 5 Bit Initial value Read/Write 7 P5 7 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W H'D8 2 P52 0 R/W 1 P51 0 R/W I/O ports 0 P50 0 R/W PDR9--Port data register 9 Bit Initial value Read/Write 7 P9 7 0 R/W 6 P96 0 R/W 5 P95 0 R/W 4 P94 0 R/W 3 P93 0 R/W H'DC 2 P92 0 R/W 1 P91 0 R/W I/O ports 0 P90 0 R/W PDRA--Port data register A Bit Initial value Read/Write 7 0 6 0 5 0 4 0 3 PA3 0 R/W H'DD 2 PA2 0 R/W 1 PA1 0 R/W I/O ports 0 PA0 0 R/W PDRB--Port data register B Bit Read/Write 7 PB7 R 6 PB6 R 5 PB5 R 4 PB4 R 3 PB3* R H'DE 2 PB2* R 1 PB1* R I/O ports 0 PB0* R Note: * PB3 to PB0 are functions of the H8/3857 Group only. In the H8/3854 Group these bits are reserved. Rev.3.00 Jul. 19, 2007 page 496 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers PUCR1--Port pull-up control register 1 Bit Initial value Read/Write 7 PUCR17 0 R/W 6 H'E0 I/O ports 5 4 3 2 1 0 * PUCR1 PUCR1 * PUCR1 * PUCR1 PUCR1 PUCR1 PUCR16 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * PUCR16, PUCR14, and PUCR13 are functions of the H8/3857 Group only. In the H8/3854 Group these bits are reserved, and must always be cleared to 0. PUCR3--Port pull-up control register 3 H'E1 I/O ports (H8/3857 Group only) 2 0 1 0 R/W 0 0 R/W Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W PUCR3 7 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 R/W PUCR5--Port pull-up control register 5 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'E2 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PCR1--Port control register 1 Bit Initial value Read/Write 7 PCR17 0 W 6 PCR16* 0 W 5 PCR15 0 W 4 0 W 3 0 W H'E4 2 PCR12 0 W 1 PCR11 0 W I/O ports 0 PCR10 0 W PCR14* PCR13* Port 1 input/output select 0 Input pin 1 Output pin Note: * PCR16, PCR14, and PCR13 are functions of the H8/3857 Group only. In the H8/3854 Group these bits are reserved, and must always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 497 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers PCR2--Port control register 2 Bit Initial value Read/Write 7 PCR27 0 W 6 PCR26 0 W 5 PCR25 0 W 4 PCR24 0 W 3 PCR23 0 W H'E5 2 PCR22 0 W 1 PCR21 0 W I/O ports 0 PCR20 0 W Port 2 input/output select 0 Input pin 1 Output pin PCR3--Port control register 3 H'E6 I/O ports (H8/3857 Group only) 2 1 PCR31 0 W 0 PCR30 0 W Bit Initial value Read/Write 7 PCR37 0 W 6 PCR36 0 W 5 PCR35 0 W 4 PCR34 0 W 3 PCR33 0 W PCR32 0 W Port 3 input/output select 0 Input pin 1 Output pin PCR4--Port control register 4 Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 1 H'E7 2 PCR42 0 W 1 PCR41 0 W I/O ports 0 PCR40 0 W Port 4 input/output select 0 Input pin 1 Output pin Rev.3.00 Jul. 19, 2007 page 498 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers PCR5--Port control register 5 Bit Initial value Read/Write 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W H'E8 2 PCR52 0 W 1 PCR51 0 W I/O ports 0 PCR50 0 W Port 5 input/output select 0 Input pin 1 Output pin PCR9--Port control register 9 Bit Initial value Read/Write 7 PCR97 0 W 6 PCR96 0 W 5 PCR95 0 W 4 PCR94 0 W 3 PCR93 0 W H'EC 2 PCR92 0 W 1 PCR91 0 W I/O ports 0 PCR90 0 W Port 9 input/output select 0 Input pin 1 Output pin PCRA--Port control register A Bit Initial value Read/Write 7 1 6 1 5 1 4 1 3 H'ED 2 PCRA 2 0 W 1 PCRA 1 0 W I/O ports 0 PCRA 0 0 W PCRA 3 0 W Port A input/output select 0 Input pin 1 Output pin Rev.3.00 Jul. 19, 2007 page 499 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers SYSCR1--System control register 1 Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W H'F0 2 1 1 1 System control 0 1 Low speed on flag 0 The CPU operates on the system clock () 1 The CPU operates on the subclock ( SUB) Standby timer select 2 to 0 0 0 0 Wait time = 8,192 states 1 Wait time = 16,384 states 1 0 Wait time = 32,768 states 1 Wait time = 65,536 states 1 * * Wait time = 131,072 states Software standby 0 When a SLEEP instruction is executed in active mode, a transition is made to sleep mode. When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode. 1 When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode. When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode. Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 500 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers SYSCR2--System control register 2 Bit Initial value Read/Write 7 1 6 1 5 1 4 NESEL 0 R/W 3 DTON 0 R/W H'F1 2 MSON 0 R/W 1 System control 0 SA0 0 R/W SA1 0 R/W Medium speed on flag 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct transfer on flag Subactive mode clock select 0 0 W/8 1 W/4 1 * W/2 0 When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. 1 When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1. Noise elimination sampling frequency select 0 Sampling rate is OSC /16 1 Sampling rate is OSC /4 Legend: * Don't care Rev.3.00 Jul. 19, 2007 page 501 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers IEGR--IRQ edge select register Bit Initial value Read/Write 7 1 6 1 5 1 4 IEG4 0 R/W 3 IEG3 0 R/W H'F2 2 IEG2* 0 R/W 1 System control 0 IEG0 0 R/W IEG1 0 R/W IRQ 0 edge select 0 Falling edge of IRQ 0 pin input is detected 1 Rising edge of IRQ 0 pin input is detected IRQ 1 edge select 0 Falling edge of IRQ 1 /TMIB pin input is detected 1 Rising edge of IRQ 1 /TMIB pin input is detected IRQ 2 edge select 0 Falling edge of IRQ 2 /TMIC pin input is detected 1 Rising edge of IRQ 2 /TMIC pin input is detected IRQ 3 edge select 0 Falling edge of IRQ 3 /TMIF pin input is detected 1 Rising edge of IRQ 3 /TMIF pin input is detected IRQ 4 edge select 0 Falling edge of IRQ 4 /ADTRG pin input is detected 1 Rising edge of IRQ 4 /ADTRG pin input is detected Note: * IEG2 is a function of the H8/3857 Group only. In the H8/3854 Group this bit is reserved, and must always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 502 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers IENR1--Interrupt enable register 1 Bit Initial value Read/Write 7 IENTA 0 R/W 6 IENS1* 0 R/W 5 IENWP 0 R/W 4 IEN4 0 R/W 3 IEN3 0 R/W H'F3 2 IEN2* 0 R/W 1 System control 0 IEN0 0 R/W IEN1 0 R/W IRQ 4 to IRQ 0 interrupt enable 0 Disables interrupt request IRQ n 1 Enables interrupt request IRQ n Note: n = 4 to 0 Wakeup interrupt enable 0 Disables interrupt requests from WKP7 to WKP0 1 Enables interrupt requests from WKP7 to WKP0 SCI1 interrupt enable 0 Disables SCI1 interrupts 1 Enables SCI1 interrupts Timer A interrupt enable 0 Disables timer A interrupts 1 Enables timer A interrupts Note: * IENS1 and IEN2 are functions of the H8/3857 Group only. In the H8/3854 Group these bits are reserved, and must always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 503 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers IENR2--Interrupt enable register 2 Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'F4 2 0 R/W 1 System control 0 IENTB 0 R/W IENTFH IENTFL IENTC* 0 R/W Timer B interrupt enable 0 Disables timer B interrupts 1 Enables timer B interrupts Timer C interrupt enable 0 Disables timer C interrupts 1 Enables timer C interrupts Timer FL interrupt enable 0 Disables timer FL interrupts 1 Enables timer FL interrupts Timer FH interrupt enable 0 Disables timer FH interrupts 1 Enables timer FH interrupts A/D converter interrupt enable 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests Direct transfer interrupt enable 0 Disables direct transfer interrupt requests 1 Enables direct transfer interrupt requests Note: * IENTC is a function of the H8/3857 Group only. In the H8/3854 Group this bit is reserved, and must always be cleared to 0. Rev.3.00 Jul. 19, 2007 page 504 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers IRR1--Interrupt request register 1 Bit Initial value Read/Write 7 IRRTA 0 R/W*2 6 IRRS1*1 0 R/W*2 5 1 4 IRRI4 0 R/W*2 3 IRRI3 0 R/W*2 H'F6 2 IRRI2*1 0 R/W*2 1 System control 0 IRRI0 0 R/W*2 IRRI1 0 R/W*2 IRQ 4 to IRQ 0 interrupt request flag 0 [Clearing conditions] When IRRI4 = 1, it is cleared by writing 0 When 0 is written to IRRI4 when IRRI4 = 1 The same also applies to IRRI3--IRRI0 1 [Setting conditions] When pin IRQ 4 is set to interrupt input and the designated signal edge is detected When pin IRQ4 is set to interrupt input and the designated edge is input at this pin The same also applies to IRRI3--IRRI0 SCI1 interrupt request flag 0 [Clearing condition] When IRRS1 = 1, it is cleared by writing 0 1 [Setting condition] When an SCI1 transfer is completed Timer A interrupt request flag 0 [Clearing condition] When IRRTA = 1, it is cleared by writing 0 1 [Setting condition] When the timer A counter overflows from H'FF to H'00 Notes: 1. IRRS1 and IRRI2 are functions of the H8/3857 Group only. In the H8/3854 Group these bits are reserved, and are always 0. 2. Only a write of 0 for flag clearing is possible. Rev.3.00 Jul. 19, 2007 page 505 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers IRR2--Interrupt request register 2 Bit Initial value Read/Write 7 IRRDT 0 R/W*2 6 IRRAD 0 R/W*2 5 0 4 0 3 0 R/W*2 H'F7 2 0 R/W*2 1 System control 0 IRRTB 0 R/W*2 IRRTFH IRRTFL IRRTC*1 0 R/W*2 Timer B interrupt request flag 0 [Clearing condition] When IRRTB = 1, it is cleared by writing 0 1 [Setting condition] When the timer B counter overflows from H'FF to H'00 Timer C interrupt request flag 0 [Clearing condition] When IRRTC = 1, it is cleared by writing 0 1 [Setting condition] When the timer C counter overflows from H'FF to H'00 or underflows from H'00 to H'FF Timer FL interrupt request flag 0 [Clearing condition] When IRRTFL = 1, it is cleared by writing 0 1 [Setting condition] When counter FL matches output compare register FL in 8-bit mode Timer FH interrupt request flag 0 [Clearing condition] When IRRTFH = 1, it is cleared by writing 0 1 [Setting condition] When counter FH matches output compare register FH in 8-bit mode, or when 16-bit counter F (TCFL, TCFH) matches 16-bit output compare register F (OCRFL, OCRFH) in 16-bit mode A/D converter interrupt request flag 0 [Clearing condition] When IRRAD = 1, it is cleared by writing 0 1 [Setting condition] When A/D conversion is completed and ADSF is reset Direct transfer interrupt request flag 0 [Clearing condition] When IRRDT = 1, it is cleared by writing 0 1 [Setting condition] A SLEEP instruction is executed when DTON = 1 and a direct transfer is made Notes: 1. IRRTC is a function of the H8/3857 Group only. In the H8/3854 Group this bit is reserved, and is always 0. 2. Only a write of 0 for flag clearing is possible. Rev.3.00 Jul. 19, 2007 page 506 of 532 REJ09B0397-0300 Appendix B Internal I/O Registers IWPR--Wakeup interrupt request register Bit Initial value Read/Write 7 IWPF7 0 R/W * 6 IWPF6 0 R/W * 5 IWPF5 0 R/W * 4 IWPF4 0 R/W * 3 H'F9 2 IWPF2 0 R/W * 1 System control 0 IWPF0 0 R/W * IWPF3 0 R/W * IWPF1 0 R/W * Wakeup interrupt request flag 0 [Clearing condition] When IWPFn = 1, it is cleared by writing 0 1 [Setting condition] When pin WKPn is set to interrupt input and a falling signal edge is detected Note: n = 7 to 0 Note: * Only a write of 0 for flag clearing is possible. Rev.3.00 Jul. 19, 2007 page 507 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Block Diagram of Port 1 SBY (low level during reset and in standby mode) Internal data bus PUCR1n* VCC VCC PMR1n* P1n PDR1n* VSS PCR1n* IRQ n - 4* Timer B module TMIB (P15) Legend: PDR1: PCR1: PMR1: PUCR1: Notes: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Timer C module TMIC (P16)* Timer F module TMIF (P17) n = 7, 6*, or 5 * P16, the timer C module (TMIC), and n = 6 (PDR16, PCR16, PMR16, PUCR16, IRQ2) are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group. Figure C.1 (a) Port 1 Block Diagram (Pins P17 to P15: H8/3857 Group, Pins P17, P15: H8/3854 Group) Rev.3.00 Jul. 19, 2007 page 508 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams PWM module PWM SBY Internal data bus PUCR14 VCC PMR14 P14 PDR14 VCC VSS PCR14 Legend: PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1 (b) Port 1 Block Diagram (Pin P14: Function of H8/3857 Group Only) Rev.3.00 Jul. 19, 2007 page 509 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams SBY Internal data bus PUCR13 VCC VCC P13 PDR13 VSS PCR13 Legend: PDR1: Port data register 1 PCR1: Port control register 1 PUCR1: Port pull-up control register 1 Figure C.1 (c) Port 1 Block Diagram (Pin P13: Function of H8/3857 Group Only) Rev.3.00 Jul. 19, 2007 page 510 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams Timer F module TMOFH (P12 ) TMOFL (P1 1 ) SBY Internal data bus PUCR1n VCC PMR1n P1n PDR1n VCC VSS PCR1n Legend: PDR1: PCR1: PMR1: PUCR1: Note: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 n = 2 or 1 Figure C.1 (d) Port 1 Block Diagram (Pins P12 and P11) Rev.3.00 Jul. 19, 2007 page 511 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams Timer A module TMOW SBY Internal data bus PUCR10 VCC PMR10 P10 PDR10 VCC VSS PCR10 Legend: PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1 (e) Port 1 Block Diagram (Pin P10) Rev.3.00 Jul. 19, 2007 page 512 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams C.2 Block Diagram of Port 2 SBY Internal data bus PMR4 n VCC P2n PDR2 n VSS PCR2 n Legend: PDR2: Port data register 2 PCR2: Port control register 2 PMR4: Port mode register 4 Notes: H8/3857 Group: n = 7 to 2 H8/3854 Group: n = 7 to 1 Figure C.2 (a) Port 2 Block Diagram (Pins P27 to P22: H8/3857 Group; Pins P27 to P21: H8/3854 Group) Rev.3.00 Jul. 19, 2007 page 513 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams SBY Internal data bus PMR4 1 VCC PMR21 P21 PDR21 VSS PCR21 Timer C module UD Legend: PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C.2 (b) Port 2 Block Diagram (Pin P21: H8/3857 Group) Rev.3.00 Jul. 19, 2007 page 514 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams SBY Internal data bus PMR4 0 VCC PMR2 0 P20 PDR20 VSS PCR2 0 IRQ 4 Legend: PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 A/D converter module ADTRG Figure C.2 (c) Port 2 Block Diagram (Pin P20) Rev.3.00 Jul. 19, 2007 page 515 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams C.3 Block Diagram of Port 3 (H8/3857 Group Only) SBY PUCR3n VCC VCC P3n PDR3n VSS PCR3n Legend: PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 Note: n = 7 to 3 Figure C.3 (a) Port 3 Block Diagram (Pins P37 to P33: Functions of H8/3857 Group Only) Rev.3.00 Jul. 19, 2007 page 516 of 532 REJ09B0397-0300 Internal data bus Appendix C I/O Port Block Diagrams SCI1 module SO 1 PMR2 2 Internal data bus PUCR32 VCC PMR3 2 P3 2 PDR3 2 SBY VCC VSS PCR3 2 Legend: PDR3: PCR3: PMR3: PMR2: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port mode register 2 Port pull-up control register 3 Figure C.3 (b) Port 3 Block Diagram (Pin P32: Function of H8/3857 Group Only) Rev.3.00 Jul. 19, 2007 page 517 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams SBY PUCR31 VCC VCC Internal data bus PMR31 P31 PDR31 VSS PCR31 SCI1 module SI1 Legend: PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (c) Port 3 Block Diagram (Pin P31: Function of H8/3857 Group Only) Rev.3.00 Jul. 19, 2007 page 518 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams SCI1 module SBY EXCK SCKO SCKI PUCR30 VCC VCC PMR30 P30 PDR30 VSS PCR30 Legend: PDR3: PCR3: PMR3: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 Figure C.3 (d) Port 3 Block Diagram (Pin P30: Function of H8/3857 Group Only) Rev.3.00 Jul. 19, 2007 page 519 of 532 REJ09B0397-0300 Internal data bus Appendix C I/O Port Block Diagrams C.4 Block Diagram of Port 4 Internal data bus PMR2 3 P4 3 IRQ 0 Legend: PMR2: Port mode register 2 Figure C.4 (a) Port 4 Block Diagram (Pin P43) SBY VCC SCI3 module TE TXD P4 2 PDR4 2 Internal data bus VSS PCR4 2 Legend: PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (b) Port 4 Block Diagram (Pin P42) Rev.3.00 Jul. 19, 2007 page 520 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams SBY SCI3 module VCC RE RXD P4 1 PDR4 1 VSS PCR4 1 Legend: PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (c) Port 4 Block Diagram (Pin P41) Rev.3.00 Jul. 19, 2007 page 521 of 532 REJ09B0397-0300 Internal data bus Appendix C I/O Port Block Diagrams SBY SCI3 module VCC SCKIE SCKOE SCKO SCKI P4 0 PDR4 0 VSS PCR4 0 Legend: PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (d) Port 4 Block Diagram (Pin P40) Rev.3.00 Jul. 19, 2007 page 522 of 532 REJ09B0397-0300 Internal data bus Appendix C I/O Port Block Diagrams C.5 Block Diagram of Port 5 SBY Internal data bus PUCR5n VCC VCC PMR5 n P5 n PDR5n VSS PCR5n WKPn Legend: PDR5: PCR5: PMR5: PUCR5: Note: Port data register 5 Port control register 5 Port mode register 5 Port pull-up control register 5 n = 7 to 0 Figure C.5 Port 5 Block Diagram Rev.3.00 Jul. 19, 2007 page 523 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams C.6 Block Diagram of Port 9 SBY Internal data bus VCC P9 n PDR9n VSS PCR9n Legend: PDR9: Port data register 9 PCR9: Port control register 9 Note: n = 7 to 0 Figure C.6 Port 9 Block Diagram Rev.3.00 Jul. 19, 2007 page 524 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams C.7 Block Diagram of Port A SBY Internal data bus VCC PDRA n PA n PCRA n VSS Legend: PDRA: Port data register A PCRA: Port control register A Note: n = 3 to 0 Figure C.7 Port A Block Diagram Rev.3.00 Jul. 19, 2007 page 525 of 532 REJ09B0397-0300 Appendix C I/O Port Block Diagrams C.8 Block Diagram of Port B Internal data bus PBn A/D module DEC AMR0 to AMR3 V IN Notes: H8/3857 Group: n = 7 to 0 H8/3854 Group: n = 7 to 4 Figure C.8 Port B Block Diagram (Pins PB7 to PB0: H8/3857 Group, Pins PB7 to PB4: H8/3854 Group) Rev.3.00 Jul. 19, 2007 page 526 of 532 REJ09B0397-0300 Appendix D Port States in the Different Processing States Appendix D Port States in the Different Processing States Table D.1 Port 1 Port States Overview Reset Sleep Subsleep Standby Retained Retained Retained Retained Retained Retained Retained Watch Subactive Active Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions P17 to P10* High Retained impedance P27 to P20 High Retained impedance High Retained impedance*2 High impedance Retained P37 to P30*1 High Retained impedance P43 to P40 P57 to P50 P97 to P90 PA3 to PA0 High Retained impedance High Retained impedance High Retained impedance High Retained impedance High Retained impedance*2 High impedance Retained High Retained 2 impedance* High impedance High impedance Retained Retained PB7 to PB0*1 High High High High impedance impedance impedance impedance High High High impedance impedance impedance Notes: 1. P16, P14, P13, P37 to P30, and PB3 to PB0 are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group. 2. High level output when MOS pull-up is in on state. Rev.3.00 Jul. 19, 2007 page 527 of 532 REJ09B0397-0300 Appendix E List of Product Codes Appendix E List of Product Codes Table E.1 H8/3857 Group Product Code Lineup Part No. Mask Code Package 144-pin QFP (FP-144H) 144-pin TQFP (TFP-144) Die Product Type H8/3857F F-ZTAT versions Standard HD64F3857FQ HD64F3857FQ models HD64F3857TG HD64F3857TG HCD64F3857 H8/3857 Mask ROM Standard HD6433857FQ HD6433857(***)FQ 144-pin QFP (FP-144H) versions models HD6433857TG HD6433857(***)TG 144-pin TQFP (TFP-144) HCD6433857 Die H8/3856 Mask ROM Standard HD6433856FQ HD6433856(***)FQ 144-pin QFP (FP-144H) versions models HD6433856TG HD6433856(***)TG 144-pin TQFP (TFP-144) HCD6433856 Die H8/3855 Mask ROM Standard HD6433855FQ HD6433855(***)FQ 144-pin QFP (FP-144H) versions models HD6433855TG HD6433855(***)TG 144-pin TQFP (TFP-144) HCD6433855 Die Table E.2 H8/3854 Group Product Code Lineup Part No. Mask Code Package 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100G) Die Product Type H8/3854F F-ZTAT versions Standard HD64F3854H HD64F3854H models HD64F3854W HD64F3854W HCD64F3854 H8/3854 Mask ROM Standard HD6433854H HD6433854(***)H 100-pin QFP (FP-100B) versions* models HD6433854W HD6433854(***)W 100-pin TQFP (TFP-100G) HCD6433854 Die H8/3853 Mask ROM Standard HD6433853H HD6433853(***)H 100-pin QFP (FP-100B) versions* models HD6433853W HD6433853(***)W 100-pin TQFP (TFP-100G) HCD6433853 Die H8/3852 Mask ROM Standard HD6433852H HD6433852(***)H 100-pin QFP (FP-100B) versions* models HD6433852W HD6433852(***)W 100-pin TQFP (TFP-100G) HCD6433852 Die Notes: For mask ROM versions, (***) is the ROM code. * Under development Rev.3.00 Jul. 19, 2007 page 528 of 532 REJ09B0397-0300 Appendix F Package Dimensions Appendix F Package Dimensions The package dimention that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KC-A Previous Code FP-144H/FP-144HV MASS[Typ.] 1.4g HD *1 D 108 109 73 72 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section 144 1 ZD Index mark 36 37 Reference Dimension in Millimeters Symbol F A1 L L1 e *3 y bp Detail F x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 20 20 1.45 21.7 22.0 22.3 21.7 22.0 22.3 1.70 0.04 0.12 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.08 0.10 1.25 1.25 0.4 0.5 0.6 1.0 Min ZE A A2 Figure F.1 FP-144H Package Dimensions Rev.3.00 Jul. 19, 2007 page 529 of 532 REJ09B0397-0300 c Appendix F Package Dimensions JEITA Package Code P-TQFP144-16x16-0.40 RENESAS Code PTQP0144LC-A Previous Code TFP-144/TFP-144V MASS[Typ.] 0.6g HD *1 D 108 109 73 72 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp *2 HE E b1 c1 c 144 1 ZD Index mark 36 37 Reference Dimension in Millimeters Symbol ZE Terminal cross section F e *3 y bp x M A1 L L1 Detail F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Min Nom Max 16 16 1.00 17.8 18.0 18.2 17.8 18.0 18.2 1.20 0.05 0.10 0.15 0.13 0.18 0.23 0.16 0.12 0.17 0.22 0.15 8 0 0.4 0.07 0.08 1.0 1.0 0.4 0.5 0.6 1.0 A A2 Figure F.2 TFP-144 Package Dimensions Rev.3.00 Jul. 19, 2007 page 530 of 532 REJ09B0397-0300 c Appendix F Package Dimensions JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g HD *1 D 75 51 76 50 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section ZE 100 26 Reference Dimension in Millimeters Symbol 1 ZD 25 F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 14 14 2.70 15.7 16.0 16.3 15.7 16.0 16.3 3.05 0.00 0.12 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.08 0.10 1.0 1.0 0.3 0.5 0.7 1.0 Min A A2 Figure F.3 FP-100B Package Dimensions Rev.3.00 Jul. 19, 2007 page 531 of 532 REJ09B0397-0300 c Appendix F Package Dimensions JEITA Package Code P-TQFP100-12x12-0.40 RENESAS Code PTQP0100LC-A Previous Code MASS[Typ.] TFP-100G/TFP-100GV 0.4g HD *1 D 75 51 76 50 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp *2 HE E b1 Reference Dimension in Millimeters Symbol c1 c 100 26 1 ZD Index mark 25 F ZE Terminal cross section e *3 y bp A1 L L1 x M Detail F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 12 12 1.00 13.8 14.0 14.2 13.8 14.0 14.2 1.20 0.00 0.10 0.20 0.13 0.18 0.23 0.16 0.12 0.17 0.22 0.15 0 8 0.4 0.07 0.10 1.2 1.2 0.4 0.5 0.6 1.0 Min A2 Figure F.4 TFP-100G Package Dimensions Rev.3.00 Jul. 19, 2007 page 532 of 532 REJ09B0397-0300 A c Renesas 8-Bit Single-Chip Microcomputer Hardware Manual H8/3857 Group, H8/3857 F-ZTATTM, H8/3854 Group, H8/3854 F-ZTATTM Publication Date: 1st Edition, March 1999 Rev.3.00, July 19, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8/3857 Group, H8/3857 F-ZTATTM, H8/3854 Group, H8/3854 F-ZTATTM Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan |
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